SF32LB (SiFli SF32LB5x) on-chip AUDCODEC driver, ported from the Zephyr RTOS driver drivers/audio/sf32lb_codec.c (https://github.com/zephyrproject-rtos/zephyr, Apache-2.0) using the register definitions from hal_sifli cmsis/sf32lb52x/audcodec.h. More...

#include <SF32LB.h>

Inheritance diagram for SF32LB:

Classes
struct	AdcClockConfig

struct	DacClockConfig
	Clock divider settings for the non-PLL (48 MHz XTAL) sample rates. More...

Public Types
enum	Reg : uint32_t { REG_ID = 0x00 , REG_CFG = 0x04 , REG_IRQ = 0x08 , REG_IRQ_MSK = 0x0C , REG_DAC_CFG = 0x10 , REG_ADC_CFG = 0x14 , REG_APB_STAT = 0x18 , REG_ADC_CH0_CFG = 0x20 , REG_ADC_CH1_CFG = 0x24 , REG_DAC_CH0_CFG = 0x30 , REG_DAC_CH0_CFG_EXT = 0x34 , REG_DAC_CH1_CFG = 0x38 , REG_DAC_CH1_CFG_EXT = 0x3C , REG_ADC_CH0_ENTRY = 0x40 , REG_ADC_CH1_ENTRY = 0x44 , REG_DAC_CH0_ENTRY = 0x50 , REG_DAC_CH1_ENTRY = 0x54 , REG_DAC_CH0_DEBUG = 0x58 , REG_DAC_CH1_DEBUG = 0x5C , REG_DAC_CH0_DC = 0x60 , REG_DAC_CH1_DC = 0x64 , REG_COMMON_CFG = 0x70 , REG_BG_CFG0 = 0x74 , REG_BG_CFG1 = 0x78 , REG_BG_CFG2 = 0x7C , REG_REFGEN_CFG = 0x80 , REG_PLL_CFG0 = 0x84 , REG_PLL_CFG1 = 0x88 , REG_PLL_CFG2 = 0x8C , REG_PLL_CFG3 = 0x90 , REG_PLL_CFG4 = 0x94 , REG_PLL_CFG5 = 0x98 , REG_PLL_CFG6 = 0x9C , REG_PLL_STAT = 0xA0 , REG_PLL_CAL_CFG = 0xA4 , REG_PLL_CAL_RESULT = 0xA8 , REG_ADC_ANA_CFG = 0xAC , REG_ADC1_CFG1 = 0xB0 , REG_ADC1_CFG2 = 0xB4 , REG_ADC2_CFG1 = 0xB8 , REG_ADC2_CFG2 = 0xBC , REG_DAC1_CFG = 0xC0 , REG_DAC2_CFG = 0xC4 }
	Register offsets (byte offsets from the AUDCODEC base address) More...

Public Member Functions
uint8_t	address ()
	Provides the actual I2C address of the codec.

virtual bool	begin (uint32_t sample_rate, uint8_t bits, codec_mode_t mode, i2s_format_t fmt, bool is_master, uint8_t channels)=0
	Initializes the codec.

bool	begin (uintptr_t base, uint32_t sample_rate=48000)

bool	beginInput (uint32_t sample_rate=48000)

virtual int	getInputVolume ()

virtual int	getVolume ()
	Provides the output volume in % (0...100) that was set with setVolume()

i2c_bus_handle_t	getWire ()
	Provides the actual I2C communication object.

virtual bool	isInputVolumeSupported ()
	Returns true if the driver supports setting the input volume, false otherwise. By default we return false, but some drivers (e.g. WM8962) override this to return true.

virtual bool	setActive (codec_mode_t mode)

void	setAddress (uint8_t addr)
	Defines the I2C address of the codec.

void	setBaseAddress (uintptr_t base)

virtual bool	setDevices (input_device_t input_device, output_device_t output_device)

virtual bool	setInputVolume (int volume)

bool	setMute (bool mute_flag) override

bool	setVolume (int volume) override

bool	setVolumeDb (int volume_db)
	Sets the DAC output volume in dB, range MIN_VOLUME_DB..MAX_VOLUME_DB.

void	setWire (i2c_bus_handle_t w)
	Defines the I2C communication object.

void	start ()
	Starts (un-mutes) the DAC output path.

void	stop ()
	Mutes and disables the DAC output path.

void	stopInput ()
	Disables the ADC input path.

Static Public Attributes
static constexpr uint32_t	ADC_ANA_CFG_MICBIAS_CHOP_EN = 1UL << 0

static constexpr uint32_t	ADC_ANA_CFG_MICBIAS_EN = 1UL << 1

static constexpr uint32_t	ADC_CFG_CLK_DIV_Msk = 0xFFUL << 8

static constexpr uint32_t	ADC_CFG_CLK_SRC_SEL_Msk = 0x1UL << 6

static constexpr uint32_t	ADC_CFG_OP_MODE_Msk = 0x3UL << 3

static constexpr uint32_t	ADC_CFG_OSR_SEL_Msk = 0x7UL << 0

static constexpr uint32_t	ADC_CFG_PATH_RESET = 1UL << 5

static constexpr uint32_t	ADC_CH_CFG_DATA_FORMAT = 1UL << 16

static constexpr uint32_t	ADC_CH_CFG_DMA_EN = 1UL << 7

static constexpr uint32_t	ADC_CH_CFG_ENABLE = 1UL << 0

static constexpr uint32_t	ADC_CH_CFG_FINE_VOL_Msk = 0xFUL << 12

static constexpr uint32_t	ADC_CH_CFG_HPF_BYPASS = 1UL << 1

static constexpr uint32_t	ADC_CH_CFG_HPF_COEF_Msk = 0xFUL << 2

static constexpr uint32_t	ADC_CH_CFG_ROUGH_VOL_Msk = 0xFUL << 8

static constexpr uint32_t	ADC_CH_CFG_STB_INV = 1UL << 6

static constexpr uint32_t	ADCx_CFG1_DACN_EN = 1UL << 21

static constexpr uint32_t	ADCx_CFG1_DIFF_EN = 1UL << 22

static constexpr uint32_t	ADCx_CFG1_FSP_Msk = 0x3UL << 23

static constexpr uint32_t	ADCx_CFG1_GC_Msk = 0x7UL << 18

static constexpr uint32_t	ADCx_CFG1_VCMST = 1UL << 3

static constexpr uint32_t	ADCx_CFG1_VREF_SEL_Msk = 0x7UL << 6

static constexpr uint32_t	ADCx_CFG2_CLEAR = 1UL << 0

static constexpr uint32_t	ADCx_CFG2_EN = 1UL << 3

static constexpr uint32_t	ADCx_CFG2_RSTB = 1UL << 2

static constexpr uint32_t	BG_CFG0_EN = 1UL << 0

static constexpr uint32_t	BG_CFG0_EN_AMP = 1UL << 12

static constexpr uint32_t	BG_CFG0_EN_RCFLT = 1UL << 8

static constexpr uint32_t	BG_CFG0_EN_SMPL = 1UL << 7

static constexpr uint32_t	BG_CFG0_LP_MODE = 1UL << 1

static constexpr uint32_t	BG_CFG0_MIC_VREF_SEL_Msk = 0x7UL << 9

static constexpr uint32_t	BG_CFG0_SET_VC = 1UL << 13

static constexpr uint32_t	BG_CFG0_VREF_SEL_Msk = 0xFUL << 2

static constexpr uint32_t	CFG_ADC_EN_DLY_SEL_Msk = 0x3UL << 3

static constexpr uint32_t	CFG_ADC_ENABLE = 1UL << 0

static constexpr uint32_t	CFG_DAC_ENABLE = 1UL << 1

static constexpr uint32_t	DAC_CFG_CLK_DIV_Msk = 0xFFUL << 8

static constexpr uint32_t	DAC_CFG_CLK_SRC_SEL_Msk = 0x1UL << 7

static constexpr uint32_t	DAC_CFG_OP_MODE_Msk = 0x3UL << 4

static constexpr uint32_t	DAC_CFG_OSR_SEL_Msk = 0xFUL << 0

static constexpr uint32_t	DAC_CFG_PATH_RESET = 1UL << 6

static constexpr uint32_t	DAC_CH_CFG_DATA_FORMAT = 1UL << 16

static constexpr uint32_t	DAC_CH_CFG_DEM_MODE_Msk = 0x3UL << 2

static constexpr uint32_t	DAC_CH_CFG_DITHER_EN = 1UL << 29

static constexpr uint32_t	DAC_CH_CFG_DITHER_GAIN_Msk = 0x7UL << 26

static constexpr uint32_t	DAC_CH_CFG_DMA_EN = 1UL << 7

static constexpr uint32_t	DAC_CH_CFG_DOUT_MUTE = 1UL << 1

static constexpr uint32_t	DAC_CH_CFG_ENABLE = 1UL << 0

static constexpr uint32_t	DAC_CH_CFG_EXT_RAMP_EN = 1UL << 0

static constexpr uint32_t	DAC_CH_CFG_EXT_RAMP_INTERVAL_Msk = 0xFUL << 3

static constexpr uint32_t	DAC_CH_CFG_EXT_RAMP_MODE = 1UL << 1

static constexpr uint32_t	DAC_CH_CFG_EXT_RAMP_STAT_Msk = 0x3UL << 7

static constexpr uint32_t	DAC_CH_CFG_EXT_ZERO_ADJUST_EN = 1UL << 2

static constexpr uint32_t	DAC_CH_CFG_FINE_VOL_Msk = 0xFUL << 12

static constexpr uint32_t	DAC_CH_CFG_ROUGH_VOL_Msk = 0xFUL << 8

static constexpr uint32_t	DAC_CH_CFG_SINC_GAIN_Msk = 0x1FFUL << 17

static constexpr uint32_t	DAC_CH_DEBUG_BYPASS = 1UL << 16

static constexpr uint32_t	DAC_CH_DEBUG_DATA_OUT_Msk = 0xFFFFUL << 0

static constexpr uint32_t	DACx_CFG_EN_AMP = 1UL << 21

static constexpr uint32_t	DACx_CFG_EN_DAC = 1UL << 25

static constexpr uint32_t	DACx_CFG_EN_OS_DAC = 1UL << 0

static constexpr uint32_t	DACx_CFG_EN_VCM = 1UL << 24

static constexpr uint32_t	DACx_CFG_LP_MODE = 1UL << 14

static constexpr uint32_t	DACx_CFG_SR = 1UL << 12

static constexpr int	MAX_VOLUME_DB = 54

static constexpr int	MIN_VOLUME_DB = -36

static constexpr uint32_t	PLL_CFG0_EN_ANA = 1UL << 15

static constexpr uint32_t	PLL_CFG0_EN_IARY = 1UL << 28

static constexpr uint32_t	PLL_CFG0_EN_VCO = 1UL << 27

static constexpr uint32_t	PLL_CFG0_ICP_SEL_Msk = 0x1FUL << 6

static constexpr uint32_t	PLL_CFG1_C2_SEL_Msk = 0x7UL << 8

static constexpr uint32_t	PLL_CFG1_CZ_SEL_Msk = 0x7UL << 11

static constexpr uint32_t	PLL_CFG1_R3_SEL_Msk = 0xFUL << 0

static constexpr uint32_t	PLL_CFG1_RZ_SEL_Msk = 0xFUL << 4

static constexpr uint32_t	PLL_CFG2_EN_DIG = 1UL << 13

static constexpr uint32_t	PLL_CFG2_RSTB = 1UL << 8

static constexpr uint32_t	PLL_CFG3_EN_SDM = 1UL << 30

static constexpr uint32_t	PLL_CFG4_DIVA_CLK_DAC_Msk = 0x1FUL << 6

static constexpr uint32_t	PLL_CFG4_DIVA_CLK_DIG_Msk = 0x1FUL << 18

static constexpr uint32_t	PLL_CFG4_EN_CLK_CHOP_DAC = 1UL << 5

static constexpr uint32_t	PLL_CFG4_EN_CLK_DAC = 1UL << 11

static constexpr uint32_t	PLL_CFG4_EN_CLK_DIG = 1UL << 23

static constexpr uint32_t	PLL_CFG4_SEL_CLK_DAC = 1UL << 12

static constexpr uint32_t	PLL_CFG4_SEL_CLK_DAC_SOURCE_Msk = 0x3UL << 13

static constexpr uint32_t	PLL_CFG4_SEL_CLK_DIG = 1UL << 15

static constexpr uint32_t	PLL_CFG5_EN_CLK_CHOP_BG = 1UL << 7

static constexpr uint32_t	PLL_CFG5_EN_CLK_CHOP_REFGEN = 1UL << 15

static constexpr uint32_t	PLL_CFG6_DIVA_CLK_ADC0_Msk = 0x7UL << 20

static constexpr uint32_t	PLL_CFG6_DIVA_CLK_ADC1_Msk = 0x7UL << 15

static constexpr uint32_t	PLL_CFG6_DIVA_CLK_ADC2_Msk = 0x7UL << 10

static constexpr uint32_t	PLL_CFG6_EN_CLK_ADC0 = 1UL << 23

static constexpr uint32_t	PLL_CFG6_EN_CLK_ADC1 = 1UL << 18

static constexpr uint32_t	PLL_CFG6_EN_CLK_ADC2 = 1UL << 13

static constexpr uint32_t	PLL_CFG6_EN_CLK_CHOP_MICBIAS = 1UL << 8

static constexpr uint32_t	PLL_CFG6_SEL_CLK_ADC0 = 1UL << 19

static constexpr uint32_t	PLL_CFG6_SEL_CLK_ADC1 = 1UL << 14

static constexpr uint32_t	PLL_CFG6_SEL_CLK_ADC2 = 1UL << 9

static constexpr uint32_t	PLL_CFG6_SEL_CLK_ADC_SOURCE = 1UL << 24

static constexpr uint32_t	PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Msk = 0x3UL << 6

static constexpr uint32_t	REFGEN_CFG_EN = 1UL << 0

static constexpr uint32_t	REFGEN_CFG_EN_CHOP = 1UL << 1

static constexpr uint32_t	REFGEN_CFG_LV_MODE = 1UL << 5

Protected Member Functions
void	clearBit (uint32_t offset, uint32_t mask)

void	closeAnalogAdcPath ()
	Powers down the analog ADC path (mirrors close_analog_adc_path()).

void	closeAnalogDacPath ()
	Powers down the analog DAC path (mirrors close_analog_dac_path()).

void	configAnalogAdcPath (const AdcClockConfig &clk)
	Configures the analog ADC bias/clock tree and enables ADC1.

void	configAnalogDacPath (const DacClockConfig &clk)
	Configures the analog DAC bias/clock tree and enables the DAC amps.

void	configDacPath (bool bypass)
	Enables/disables the digital bypass path on both DAC channels.

void	configRxChannel (const AdcClockConfig &clk)
	Configures the digital ADC channel 0 path (DMA disabled).

void	configTxChannel (const DacClockConfig &clk)

void	mute (bool mute_flag)

void	pllAndReferencesOn ()

uint32_t	read32 (uint32_t offset)

bool	readReg (uint8_t reg, uint8_t &value)
	Reads a single byte from an 8 bit register address.

bool	readReg16 (uint8_t reg, uint16_t &value)
	Reads a 16 bit (big endian) value from an 8 bit register address.

void	refgenInit ()

void	setBit (uint32_t offset, uint32_t mask)

bool	updateReg (uint8_t reg, uint8_t mask, uint8_t value)
	Read-Modify-Write of a single byte register.

bool	updateReg16 (uint8_t reg, uint16_t mask, uint16_t value)
	Read-Modify-Write of a 16 bit (big endian) register.

void	updateReg32 (uint32_t offset, uint32_t mask, uint32_t value)
	Read-Modify-Write of selected bits of a 32 bit register.

void	write32 (uint32_t offset, uint32_t value)

bool	writeReg (uint8_t reg, uint8_t value)
	Writes a single byte to an 8 bit register address.

bool	writeReg16 (uint8_t reg, uint16_t value)
	Writes a 16 bit (big endian) value to an 8 bit register address.

Static Protected Member Functions
static const AdcClockConfig *	adcClockConfig (uint32_t sample_rate)

static const DacClockConfig *	dacClockConfig (uint32_t sample_rate)

Protected Attributes
uint8_t	i2c_addr = 0

int	input_volume_percent = 100
	Last input volume (in %) provided to setInputVolume()

uint32_t	last_fine_vol = 0

uintptr_t	reg_base = 0

int	volume_percent = 100
	Last volume (in %) provided to setVolume()

i2c_bus_handle_t	wire = nullptr

Detailed Description

SF32LB (SiFli SF32LB5x) on-chip AUDCODEC driver, ported from the Zephyr RTOS driver drivers/audio/sf32lb_codec.c (https://github.com/zephyrproject-rtos/zephyr, Apache-2.0) using the register definitions from hal_sifli cmsis/sf32lb52x/audcodec.h.

Unlike the other codecs in this library, the SF32LB AUDCODEC is a memory mapped peripheral that is part of the SoC itself - there is no I2C control bus. It therefore extends ZephyrDriver (for API consistency) but does not use the wire/i2c_addr members; instead it operates on a 32 bit register block whose base address is provided via begin().

Only the register level audio path setup (analog DAC/ADC bias, clock dividers for the non-PLL sample rates 8/12/16/24/32/48 kHz, channel enable, volume and mute) is implemented. The fractional audio PLL (needed for the 44.1 kHz family and for PLL based clocking) requires factory trim/calibration data and SoC specific calibration routines that are out of scope for a register level port; CODEC_CLK_USING_PLL is therefore always treated as 0 (XTAL 48 MHz reference).

Member Enumeration Documentation

◆ Reg

enum Reg : uint32_t

Register offsets (byte offsets from the AUDCODEC base address)

Enumerator
REG_ID
REG_CFG
REG_IRQ
REG_IRQ_MSK
REG_DAC_CFG
REG_ADC_CFG
REG_APB_STAT
REG_ADC_CH0_CFG
REG_ADC_CH1_CFG
REG_DAC_CH0_CFG
REG_DAC_CH0_CFG_EXT
REG_DAC_CH1_CFG
REG_DAC_CH1_CFG_EXT
REG_ADC_CH0_ENTRY
REG_ADC_CH1_ENTRY
REG_DAC_CH0_ENTRY
REG_DAC_CH1_ENTRY
REG_DAC_CH0_DEBUG
REG_DAC_CH1_DEBUG
REG_DAC_CH0_DC
REG_DAC_CH1_DC
REG_COMMON_CFG
REG_BG_CFG0
REG_BG_CFG1
REG_BG_CFG2
REG_REFGEN_CFG
REG_PLL_CFG0
REG_PLL_CFG1
REG_PLL_CFG2
REG_PLL_CFG3
REG_PLL_CFG4
REG_PLL_CFG5
REG_PLL_CFG6
REG_PLL_STAT
REG_PLL_CAL_CFG
REG_PLL_CAL_RESULT
REG_ADC_ANA_CFG
REG_ADC1_CFG1
REG_ADC1_CFG2
REG_ADC2_CFG1
REG_ADC2_CFG2
REG_DAC1_CFG
REG_DAC2_CFG

Member Function Documentation

◆ adcClockConfig()

static const AdcClockConfig * adcClockConfig ( uint32_t sample_rate )

inlinestaticprotected

◆ address()

uint8_t address ( )

inlineinherited

Provides the actual I2C address of the codec.

◆ begin() [1/2]

virtual bool begin	(	uint32_t	sample_rate,
		uint8_t	bits,
		codec_mode_t	mode,
		i2s_format_t	fmt,
		bool	is_master,
		uint8_t	channels
	)

pure virtualinherited

Initializes the codec.

Implemented in AW88298, DA7212, MAX98091, PCM1681, TAS2563, TAS6422DAC, TLV320AIC3110, TLV320DAC310x, WM8904, and WM8962.

◆ begin() [2/2]

bool begin	(	uintptr_t	base,
		uint32_t	sample_rate = `48000`
	)

inline

Initializes the analog references (bandgap/refgen/PLL digital clocks) and configures the DAC output path for the given sample rate.

Parameters

base	AUDCODEC peripheral base address
sample_rate	one of 8000, 12000, 16000, 24000, 32000, 48000

◆ beginInput()

bool beginInput ( uint32_t sample_rate = 48000 )

inline

Configures and enables the ADC input path for the given sample rate. begin() must have been called first (for the shared bandgap/refgen).

◆ clearBit()

void clearBit	(	uint32_t	offset,
		uint32_t	mask
	)

inlineprotected

◆ closeAnalogAdcPath()

void closeAnalogAdcPath ( )

inlineprotected

Powers down the analog ADC path (mirrors close_analog_adc_path()).

◆ closeAnalogDacPath()

void closeAnalogDacPath ( )

inlineprotected

Powers down the analog DAC path (mirrors close_analog_dac_path()).

◆ configAnalogAdcPath()

void configAnalogAdcPath ( const AdcClockConfig & clk )

inlineprotected

Configures the analog ADC bias/clock tree and enables ADC1.

◆ configAnalogDacPath()

void configAnalogDacPath ( const DacClockConfig & clk )

inlineprotected

Configures the analog DAC bias/clock tree and enables the DAC amps.

◆ configDacPath()

void configDacPath ( bool bypass )

inlineprotected

Enables/disables the digital bypass path on both DAC channels.

◆ configRxChannel()

void configRxChannel ( const AdcClockConfig & clk )

inlineprotected

Configures the digital ADC channel 0 path (DMA disabled).

◆ configTxChannel()

void configTxChannel ( const DacClockConfig & clk )

inlineprotected

Configures the digital DAC channel 0 path (DMA disabled - data is fed via DAC_CH0_ENTRY or, if bypass is used, DAC_CH0_DEBUG).

◆ dacClockConfig()

static const DacClockConfig * dacClockConfig ( uint32_t sample_rate )

inlinestaticprotected

◆ getInputVolume()

virtual int getInputVolume ( )

inlinevirtualinherited

Provides the input volume in % (0...100) that was set with setInputVolume()

◆ getVolume()

virtual int getVolume ( )

inlinevirtualinherited

Provides the output volume in % (0...100) that was set with setVolume()

◆ getWire()

i2c_bus_handle_t getWire ( )

inlineinherited

Provides the actual I2C communication object.

◆ isInputVolumeSupported()

virtual bool isInputVolumeSupported ( )

inlinevirtualinherited

Returns true if the driver supports setting the input volume, false otherwise. By default we return false, but some drivers (e.g. WM8962) override this to return true.

Reimplemented in DA7212, WM8904, and WM8962.

◆ mute()

void mute ( bool mute_flag )

inlineprotected

Mutes/unmutes DAC channel 0 by forcing the fine volume to its mute value (0xF) and restoring the previous value on unmute (mirrors mute_dac_path()).

◆ pllAndReferencesOn()

void pllAndReferencesOn ( )

inlineprotected

Enables the bandgap reference, reference generator and PLL digital clocks (no PLL frequency calibration, see class documentation).

◆ read32()

uint32_t read32 ( uint32_t offset )

inlineprotected

◆ readReg()

bool readReg	(	uint8_t	reg,
		uint8_t &	value
	)

inlineprotectedinherited

Reads a single byte from an 8 bit register address.

◆ readReg16()

bool readReg16	(	uint8_t	reg,
		uint16_t &	value
	)

inlineprotectedinherited

Reads a 16 bit (big endian) value from an 8 bit register address.

◆ refgenInit()

void refgenInit ( )

inlineprotected

◆ setActive()

virtual bool setActive ( codec_mode_t mode )

inlinevirtualinherited

Activates/deactivates the playback and/or capture path at runtime (without reconfiguring the codec), based on codec_mode_t (CODEC_MODE_DECODE: playback active, CODEC_MODE_ENCODE: capture active). By default this just mutes/unmutes all outputs depending on CODEC_MODE_DECODE; chip specific subclasses that support muting the input path independently override this to also mute/unmute the capture path depending on CODEC_MODE_ENCODE.

Reimplemented in DA7212, WM8904, and WM8962.

◆ setAddress()

void setAddress ( uint8_t addr )

inlineinherited

Defines the I2C address of the codec.

◆ setBaseAddress()

void setBaseAddress ( uintptr_t base )

inline

Provides the (memory mapped) base address of the AUDCODEC register block. Must be called before begin().

◆ setBit()

void setBit	(	uint32_t	offset,
		uint32_t	mask
	)

inlineprotected

◆ setDevices()

virtual bool setDevices	(	input_device_t	input_device,
		output_device_t	output_device
	)

inlinevirtualinherited

Selects the ADC input source / DAC output destination. By default this is a no-op; chip specific subclasses that support input/output routing override this to configure the corresponding registers.

Reimplemented in DA7212, MAX98091, TAS6422DAC, TLV320AIC3110, TLV320DAC310x, WM8904, and WM8962.

◆ setInputVolume()

virtual bool setInputVolume ( int volume )

inlinevirtualinherited

Defines the input volume in % (0...100). Chip specific subclasses map this to their native input volume range.

Reimplemented in DA7212, WM8904, and WM8962.

◆ setMute()

bool setMute ( bool mute_flag )

inlineoverridevirtual

Mutes/unmutes the DAC output (channel 0). The previous fine volume setting is restored when un-muting.

Reimplemented from ZephyrDriverCommon.

◆ setVolume()

bool setVolume ( int volume )

inlineoverridevirtual

Sets the DAC output volume in % (0...100), mapped to [MIN_VOLUME_DB..MAX_VOLUME_DB]

Reimplemented from ZephyrDriverCommon.

◆ setVolumeDb()

bool setVolumeDb ( int volume_db )

inline

Sets the DAC output volume in dB, range MIN_VOLUME_DB..MAX_VOLUME_DB.

◆ setWire()

void setWire ( i2c_bus_handle_t w )

inlineinherited

Defines the I2C communication object.

◆ start()

void start ( )

inline

Starts (un-mutes) the DAC output path.

◆ stop()

void stop ( )

inline

Mutes and disables the DAC output path.

◆ stopInput()

void stopInput ( )

inline

Disables the ADC input path.

◆ updateReg()

bool updateReg	(	uint8_t	reg,
		uint8_t	mask,
		uint8_t	value
	)

inlineprotectedinherited

Read-Modify-Write of a single byte register.

◆ updateReg16()

bool updateReg16	(	uint8_t	reg,
		uint16_t	mask,
		uint16_t	value
	)

inlineprotectedinherited

Read-Modify-Write of a 16 bit (big endian) register.

◆ updateReg32()

void updateReg32	(	uint32_t	offset,
		uint32_t	mask,
		uint32_t	value
	)

inlineprotected

Read-Modify-Write of selected bits of a 32 bit register.

◆ write32()

void write32	(	uint32_t	offset,
		uint32_t	value
	)

inlineprotected

◆ writeReg()

bool writeReg	(	uint8_t	reg,
		uint8_t	value
	)

inlineprotectedinherited

Writes a single byte to an 8 bit register address.

◆ writeReg16()

bool writeReg16	(	uint8_t	reg,
		uint16_t	value
	)

inlineprotectedinherited

Writes a 16 bit (big endian) value to an 8 bit register address.

Member Data Documentation

◆ ADC_ANA_CFG_MICBIAS_CHOP_EN

constexpr uint32_t ADC_ANA_CFG_MICBIAS_CHOP_EN = 1UL << 0

staticconstexpr

◆ ADC_ANA_CFG_MICBIAS_EN

constexpr uint32_t ADC_ANA_CFG_MICBIAS_EN = 1UL << 1

staticconstexpr

◆ ADC_CFG_CLK_DIV_Msk

constexpr uint32_t ADC_CFG_CLK_DIV_Msk = 0xFFUL << 8

staticconstexpr

◆ ADC_CFG_CLK_SRC_SEL_Msk

constexpr uint32_t ADC_CFG_CLK_SRC_SEL_Msk = 0x1UL << 6

staticconstexpr

◆ ADC_CFG_OP_MODE_Msk

constexpr uint32_t ADC_CFG_OP_MODE_Msk = 0x3UL << 3

staticconstexpr

◆ ADC_CFG_OSR_SEL_Msk

constexpr uint32_t ADC_CFG_OSR_SEL_Msk = 0x7UL << 0

staticconstexpr

◆ ADC_CFG_PATH_RESET

constexpr uint32_t ADC_CFG_PATH_RESET = 1UL << 5

staticconstexpr

◆ ADC_CH_CFG_DATA_FORMAT

constexpr uint32_t ADC_CH_CFG_DATA_FORMAT = 1UL << 16

staticconstexpr

◆ ADC_CH_CFG_DMA_EN

constexpr uint32_t ADC_CH_CFG_DMA_EN = 1UL << 7

staticconstexpr

◆ ADC_CH_CFG_ENABLE

constexpr uint32_t ADC_CH_CFG_ENABLE = 1UL << 0

staticconstexpr

◆ ADC_CH_CFG_FINE_VOL_Msk

constexpr uint32_t ADC_CH_CFG_FINE_VOL_Msk = 0xFUL << 12

staticconstexpr

◆ ADC_CH_CFG_HPF_BYPASS

constexpr uint32_t ADC_CH_CFG_HPF_BYPASS = 1UL << 1

staticconstexpr

◆ ADC_CH_CFG_HPF_COEF_Msk

constexpr uint32_t ADC_CH_CFG_HPF_COEF_Msk = 0xFUL << 2

staticconstexpr

◆ ADC_CH_CFG_ROUGH_VOL_Msk

constexpr uint32_t ADC_CH_CFG_ROUGH_VOL_Msk = 0xFUL << 8

staticconstexpr

◆ ADC_CH_CFG_STB_INV

constexpr uint32_t ADC_CH_CFG_STB_INV = 1UL << 6

staticconstexpr

◆ ADCx_CFG1_DACN_EN

constexpr uint32_t ADCx_CFG1_DACN_EN = 1UL << 21

staticconstexpr

◆ ADCx_CFG1_DIFF_EN

constexpr uint32_t ADCx_CFG1_DIFF_EN = 1UL << 22

staticconstexpr

◆ ADCx_CFG1_FSP_Msk

constexpr uint32_t ADCx_CFG1_FSP_Msk = 0x3UL << 23

staticconstexpr

◆ ADCx_CFG1_GC_Msk

constexpr uint32_t ADCx_CFG1_GC_Msk = 0x7UL << 18

staticconstexpr

◆ ADCx_CFG1_VCMST

constexpr uint32_t ADCx_CFG1_VCMST = 1UL << 3

staticconstexpr

◆ ADCx_CFG1_VREF_SEL_Msk

constexpr uint32_t ADCx_CFG1_VREF_SEL_Msk = 0x7UL << 6

staticconstexpr

◆ ADCx_CFG2_CLEAR

constexpr uint32_t ADCx_CFG2_CLEAR = 1UL << 0

staticconstexpr

◆ ADCx_CFG2_EN

constexpr uint32_t ADCx_CFG2_EN = 1UL << 3

staticconstexpr

◆ ADCx_CFG2_RSTB

constexpr uint32_t ADCx_CFG2_RSTB = 1UL << 2

staticconstexpr

◆ BG_CFG0_EN

constexpr uint32_t BG_CFG0_EN = 1UL << 0

staticconstexpr

◆ BG_CFG0_EN_AMP

constexpr uint32_t BG_CFG0_EN_AMP = 1UL << 12

staticconstexpr

◆ BG_CFG0_EN_RCFLT

constexpr uint32_t BG_CFG0_EN_RCFLT = 1UL << 8

staticconstexpr

◆ BG_CFG0_EN_SMPL

constexpr uint32_t BG_CFG0_EN_SMPL = 1UL << 7

staticconstexpr

◆ BG_CFG0_LP_MODE

constexpr uint32_t BG_CFG0_LP_MODE = 1UL << 1

staticconstexpr

◆ BG_CFG0_MIC_VREF_SEL_Msk

constexpr uint32_t BG_CFG0_MIC_VREF_SEL_Msk = 0x7UL << 9

staticconstexpr

◆ BG_CFG0_SET_VC

constexpr uint32_t BG_CFG0_SET_VC = 1UL << 13

staticconstexpr

◆ BG_CFG0_VREF_SEL_Msk

constexpr uint32_t BG_CFG0_VREF_SEL_Msk = 0xFUL << 2

staticconstexpr

◆ CFG_ADC_EN_DLY_SEL_Msk

constexpr uint32_t CFG_ADC_EN_DLY_SEL_Msk = 0x3UL << 3

staticconstexpr

◆ CFG_ADC_ENABLE

constexpr uint32_t CFG_ADC_ENABLE = 1UL << 0

staticconstexpr

◆ CFG_DAC_ENABLE

constexpr uint32_t CFG_DAC_ENABLE = 1UL << 1

staticconstexpr

◆ DAC_CFG_CLK_DIV_Msk

constexpr uint32_t DAC_CFG_CLK_DIV_Msk = 0xFFUL << 8

staticconstexpr

◆ DAC_CFG_CLK_SRC_SEL_Msk

constexpr uint32_t DAC_CFG_CLK_SRC_SEL_Msk = 0x1UL << 7

staticconstexpr

◆ DAC_CFG_OP_MODE_Msk

constexpr uint32_t DAC_CFG_OP_MODE_Msk = 0x3UL << 4

staticconstexpr

◆ DAC_CFG_OSR_SEL_Msk

constexpr uint32_t DAC_CFG_OSR_SEL_Msk = 0xFUL << 0

staticconstexpr

◆ DAC_CFG_PATH_RESET

constexpr uint32_t DAC_CFG_PATH_RESET = 1UL << 6

staticconstexpr

◆ DAC_CH_CFG_DATA_FORMAT

constexpr uint32_t DAC_CH_CFG_DATA_FORMAT = 1UL << 16

staticconstexpr

◆ DAC_CH_CFG_DEM_MODE_Msk

constexpr uint32_t DAC_CH_CFG_DEM_MODE_Msk = 0x3UL << 2

staticconstexpr

◆ DAC_CH_CFG_DITHER_EN

constexpr uint32_t DAC_CH_CFG_DITHER_EN = 1UL << 29

staticconstexpr

◆ DAC_CH_CFG_DITHER_GAIN_Msk

constexpr uint32_t DAC_CH_CFG_DITHER_GAIN_Msk = 0x7UL << 26

staticconstexpr

◆ DAC_CH_CFG_DMA_EN

constexpr uint32_t DAC_CH_CFG_DMA_EN = 1UL << 7

staticconstexpr

◆ DAC_CH_CFG_DOUT_MUTE

constexpr uint32_t DAC_CH_CFG_DOUT_MUTE = 1UL << 1

staticconstexpr

◆ DAC_CH_CFG_ENABLE

constexpr uint32_t DAC_CH_CFG_ENABLE = 1UL << 0

staticconstexpr

◆ DAC_CH_CFG_EXT_RAMP_EN

constexpr uint32_t DAC_CH_CFG_EXT_RAMP_EN = 1UL << 0

staticconstexpr

◆ DAC_CH_CFG_EXT_RAMP_INTERVAL_Msk

constexpr uint32_t DAC_CH_CFG_EXT_RAMP_INTERVAL_Msk = 0xFUL << 3

staticconstexpr

◆ DAC_CH_CFG_EXT_RAMP_MODE

constexpr uint32_t DAC_CH_CFG_EXT_RAMP_MODE = 1UL << 1

staticconstexpr

◆ DAC_CH_CFG_EXT_RAMP_STAT_Msk

constexpr uint32_t DAC_CH_CFG_EXT_RAMP_STAT_Msk = 0x3UL << 7

staticconstexpr

◆ DAC_CH_CFG_EXT_ZERO_ADJUST_EN

constexpr uint32_t DAC_CH_CFG_EXT_ZERO_ADJUST_EN = 1UL << 2

staticconstexpr

◆ DAC_CH_CFG_FINE_VOL_Msk

constexpr uint32_t DAC_CH_CFG_FINE_VOL_Msk = 0xFUL << 12

staticconstexpr

◆ DAC_CH_CFG_ROUGH_VOL_Msk

constexpr uint32_t DAC_CH_CFG_ROUGH_VOL_Msk = 0xFUL << 8

staticconstexpr

◆ DAC_CH_CFG_SINC_GAIN_Msk

constexpr uint32_t DAC_CH_CFG_SINC_GAIN_Msk = 0x1FFUL << 17

staticconstexpr

◆ DAC_CH_DEBUG_BYPASS

constexpr uint32_t DAC_CH_DEBUG_BYPASS = 1UL << 16

staticconstexpr

◆ DAC_CH_DEBUG_DATA_OUT_Msk

constexpr uint32_t DAC_CH_DEBUG_DATA_OUT_Msk = 0xFFFFUL << 0

staticconstexpr

◆ DACx_CFG_EN_AMP

constexpr uint32_t DACx_CFG_EN_AMP = 1UL << 21

staticconstexpr

◆ DACx_CFG_EN_DAC

constexpr uint32_t DACx_CFG_EN_DAC = 1UL << 25

staticconstexpr

◆ DACx_CFG_EN_OS_DAC

constexpr uint32_t DACx_CFG_EN_OS_DAC = 1UL << 0

staticconstexpr

◆ DACx_CFG_EN_VCM

constexpr uint32_t DACx_CFG_EN_VCM = 1UL << 24

staticconstexpr

◆ DACx_CFG_LP_MODE

constexpr uint32_t DACx_CFG_LP_MODE = 1UL << 14

staticconstexpr

◆ DACx_CFG_SR

constexpr uint32_t DACx_CFG_SR = 1UL << 12

staticconstexpr

◆ i2c_addr

uint8_t i2c_addr = 0

protectedinherited

◆ input_volume_percent

int input_volume_percent = 100

protectedinherited

Last input volume (in %) provided to setInputVolume()

◆ last_fine_vol

uint32_t last_fine_vol = 0

protected

◆ MAX_VOLUME_DB

constexpr int MAX_VOLUME_DB = 54

staticconstexpr

◆ MIN_VOLUME_DB

constexpr int MIN_VOLUME_DB = -36

staticconstexpr

DAC volume range (1 dB units): -36 dB .. +54 dB, applied via rough (6 dB step) + fine (0.5 dB step) volume fields.

◆ PLL_CFG0_EN_ANA

constexpr uint32_t PLL_CFG0_EN_ANA = 1UL << 15

staticconstexpr

◆ PLL_CFG0_EN_IARY

constexpr uint32_t PLL_CFG0_EN_IARY = 1UL << 28

staticconstexpr

◆ PLL_CFG0_EN_VCO

constexpr uint32_t PLL_CFG0_EN_VCO = 1UL << 27

staticconstexpr

◆ PLL_CFG0_ICP_SEL_Msk

constexpr uint32_t PLL_CFG0_ICP_SEL_Msk = 0x1FUL << 6

staticconstexpr

◆ PLL_CFG1_C2_SEL_Msk

constexpr uint32_t PLL_CFG1_C2_SEL_Msk = 0x7UL << 8

staticconstexpr

◆ PLL_CFG1_CZ_SEL_Msk

constexpr uint32_t PLL_CFG1_CZ_SEL_Msk = 0x7UL << 11

staticconstexpr

◆ PLL_CFG1_R3_SEL_Msk

constexpr uint32_t PLL_CFG1_R3_SEL_Msk = 0xFUL << 0

staticconstexpr

◆ PLL_CFG1_RZ_SEL_Msk

constexpr uint32_t PLL_CFG1_RZ_SEL_Msk = 0xFUL << 4

staticconstexpr

◆ PLL_CFG2_EN_DIG

constexpr uint32_t PLL_CFG2_EN_DIG = 1UL << 13

staticconstexpr

◆ PLL_CFG2_RSTB

constexpr uint32_t PLL_CFG2_RSTB = 1UL << 8

staticconstexpr

◆ PLL_CFG3_EN_SDM

constexpr uint32_t PLL_CFG3_EN_SDM = 1UL << 30

staticconstexpr

◆ PLL_CFG4_DIVA_CLK_DAC_Msk

constexpr uint32_t PLL_CFG4_DIVA_CLK_DAC_Msk = 0x1FUL << 6

staticconstexpr

◆ PLL_CFG4_DIVA_CLK_DIG_Msk

constexpr uint32_t PLL_CFG4_DIVA_CLK_DIG_Msk = 0x1FUL << 18

staticconstexpr

◆ PLL_CFG4_EN_CLK_CHOP_DAC

constexpr uint32_t PLL_CFG4_EN_CLK_CHOP_DAC = 1UL << 5

staticconstexpr

◆ PLL_CFG4_EN_CLK_DAC

constexpr uint32_t PLL_CFG4_EN_CLK_DAC = 1UL << 11

staticconstexpr

◆ PLL_CFG4_EN_CLK_DIG

constexpr uint32_t PLL_CFG4_EN_CLK_DIG = 1UL << 23

staticconstexpr

◆ PLL_CFG4_SEL_CLK_DAC

constexpr uint32_t PLL_CFG4_SEL_CLK_DAC = 1UL << 12

staticconstexpr

◆ PLL_CFG4_SEL_CLK_DAC_SOURCE_Msk

constexpr uint32_t PLL_CFG4_SEL_CLK_DAC_SOURCE_Msk = 0x3UL << 13

staticconstexpr

◆ PLL_CFG4_SEL_CLK_DIG

constexpr uint32_t PLL_CFG4_SEL_CLK_DIG = 1UL << 15

staticconstexpr

◆ PLL_CFG5_EN_CLK_CHOP_BG

constexpr uint32_t PLL_CFG5_EN_CLK_CHOP_BG = 1UL << 7

staticconstexpr

◆ PLL_CFG5_EN_CLK_CHOP_REFGEN

constexpr uint32_t PLL_CFG5_EN_CLK_CHOP_REFGEN = 1UL << 15

staticconstexpr

◆ PLL_CFG6_DIVA_CLK_ADC0_Msk

constexpr uint32_t PLL_CFG6_DIVA_CLK_ADC0_Msk = 0x7UL << 20

staticconstexpr

◆ PLL_CFG6_DIVA_CLK_ADC1_Msk

constexpr uint32_t PLL_CFG6_DIVA_CLK_ADC1_Msk = 0x7UL << 15

staticconstexpr

◆ PLL_CFG6_DIVA_CLK_ADC2_Msk

constexpr uint32_t PLL_CFG6_DIVA_CLK_ADC2_Msk = 0x7UL << 10

staticconstexpr

◆ PLL_CFG6_EN_CLK_ADC0

constexpr uint32_t PLL_CFG6_EN_CLK_ADC0 = 1UL << 23

staticconstexpr

◆ PLL_CFG6_EN_CLK_ADC1

constexpr uint32_t PLL_CFG6_EN_CLK_ADC1 = 1UL << 18

staticconstexpr

◆ PLL_CFG6_EN_CLK_ADC2

constexpr uint32_t PLL_CFG6_EN_CLK_ADC2 = 1UL << 13

staticconstexpr

◆ PLL_CFG6_EN_CLK_CHOP_MICBIAS

constexpr uint32_t PLL_CFG6_EN_CLK_CHOP_MICBIAS = 1UL << 8

staticconstexpr

◆ PLL_CFG6_SEL_CLK_ADC0

constexpr uint32_t PLL_CFG6_SEL_CLK_ADC0 = 1UL << 19

staticconstexpr

◆ PLL_CFG6_SEL_CLK_ADC1

constexpr uint32_t PLL_CFG6_SEL_CLK_ADC1 = 1UL << 14

staticconstexpr

◆ PLL_CFG6_SEL_CLK_ADC2

constexpr uint32_t PLL_CFG6_SEL_CLK_ADC2 = 1UL << 9

staticconstexpr

◆ PLL_CFG6_SEL_CLK_ADC_SOURCE

constexpr uint32_t PLL_CFG6_SEL_CLK_ADC_SOURCE = 1UL << 24

staticconstexpr

◆ PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Msk

constexpr uint32_t PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Msk = 0x3UL << 6

staticconstexpr

◆ REFGEN_CFG_EN

constexpr uint32_t REFGEN_CFG_EN = 1UL << 0

staticconstexpr

◆ REFGEN_CFG_EN_CHOP

constexpr uint32_t REFGEN_CFG_EN_CHOP = 1UL << 1

staticconstexpr

◆ REFGEN_CFG_LV_MODE

constexpr uint32_t REFGEN_CFG_LV_MODE = 1UL << 5

staticconstexpr

◆ reg_base

uintptr_t reg_base = 0

protected

◆ volume_percent

int volume_percent = 100

protectedinherited

Last volume (in %) provided to setVolume()

◆ wire

i2c_bus_handle_t wire = nullptr

protectedinherited

The documentation for this class was generated from the following file:

src/Codecs/sf32lb/SF32LB.h

Classes

Public Types

Public Member Functions

Static Public Attributes

Protected Member Functions

Static Protected Member Functions

Protected Attributes

Detailed Description

Member Enumeration Documentation

◆ Reg

Member Function Documentation

◆ adcClockConfig()

◆ address()

◆ begin() [1/2]

◆ begin() [2/2]

◆ beginInput()

◆ clearBit()

◆ closeAnalogAdcPath()

◆ closeAnalogDacPath()

◆ configAnalogAdcPath()

◆ configAnalogDacPath()

◆ configDacPath()

◆ configRxChannel()

◆ configTxChannel()

◆ dacClockConfig()

◆ getInputVolume()

◆ getVolume()

◆ getWire()

◆ isInputVolumeSupported()

◆ mute()

◆ pllAndReferencesOn()

◆ read32()

◆ readReg()

◆ readReg16()

◆ refgenInit()

◆ setActive()

◆ setAddress()

◆ setBaseAddress()

◆ setBit()

◆ setDevices()

◆ setInputVolume()

◆ setMute()

◆ setVolume()

◆ setVolumeDb()

◆ setWire()

◆ start()

◆ stop()

◆ stopInput()

◆ updateReg()

◆ updateReg16()

◆ updateReg32()

◆ write32()

◆ writeReg()

◆ writeReg16()

Member Data Documentation

◆ ADC_ANA_CFG_MICBIAS_CHOP_EN

◆ ADC_ANA_CFG_MICBIAS_EN

◆ ADC_CFG_CLK_DIV_Msk

◆ ADC_CFG_CLK_SRC_SEL_Msk

◆ ADC_CFG_OP_MODE_Msk

◆ ADC_CFG_OSR_SEL_Msk

◆ ADC_CFG_PATH_RESET

◆ ADC_CH_CFG_DATA_FORMAT

◆ ADC_CH_CFG_DMA_EN

◆ ADC_CH_CFG_ENABLE

◆ ADC_CH_CFG_FINE_VOL_Msk

◆ ADC_CH_CFG_HPF_BYPASS

◆ ADC_CH_CFG_HPF_COEF_Msk

◆ ADC_CH_CFG_ROUGH_VOL_Msk

◆ ADC_CH_CFG_STB_INV

◆ ADCx_CFG1_DACN_EN

◆ ADCx_CFG1_DIFF_EN

◆ ADCx_CFG1_FSP_Msk

◆ ADCx_CFG1_GC_Msk

◆ ADCx_CFG1_VCMST

◆ ADCx_CFG1_VREF_SEL_Msk

◆ ADCx_CFG2_CLEAR

◆ ADCx_CFG2_EN

◆ ADCx_CFG2_RSTB

◆ BG_CFG0_EN