| ADC_ANA_CFG_MICBIAS_CHOP_EN | SF32LB | static |
| ADC_ANA_CFG_MICBIAS_EN | SF32LB | static |
| ADC_CFG_CLK_DIV_Msk | SF32LB | static |
| ADC_CFG_CLK_SRC_SEL_Msk | SF32LB | static |
| ADC_CFG_OP_MODE_Msk | SF32LB | static |
| ADC_CFG_OSR_SEL_Msk | SF32LB | static |
| ADC_CFG_PATH_RESET | SF32LB | static |
| ADC_CH_CFG_DATA_FORMAT | SF32LB | static |
| ADC_CH_CFG_DMA_EN | SF32LB | static |
| ADC_CH_CFG_ENABLE | SF32LB | static |
| ADC_CH_CFG_FINE_VOL_Msk | SF32LB | static |
| ADC_CH_CFG_HPF_BYPASS | SF32LB | static |
| ADC_CH_CFG_HPF_COEF_Msk | SF32LB | static |
| ADC_CH_CFG_ROUGH_VOL_Msk | SF32LB | static |
| ADC_CH_CFG_STB_INV | SF32LB | static |
| adcClockConfig(uint32_t sample_rate) | SF32LB | inlineprotectedstatic |
| ADCx_CFG1_DACN_EN | SF32LB | static |
| ADCx_CFG1_DIFF_EN | SF32LB | static |
| ADCx_CFG1_FSP_Msk | SF32LB | static |
| ADCx_CFG1_GC_Msk | SF32LB | static |
| ADCx_CFG1_VCMST | SF32LB | static |
| ADCx_CFG1_VREF_SEL_Msk | SF32LB | static |
| ADCx_CFG2_CLEAR | SF32LB | static |
| ADCx_CFG2_EN | SF32LB | static |
| ADCx_CFG2_RSTB | SF32LB | static |
| address() | ZephyrDriverCommon | inline |
| begin(uintptr_t base, uint32_t sample_rate=48000) | SF32LB | inline |
| audio_driver::ZephyrDriverCommon::begin(uint32_t sample_rate, uint8_t bits, codec_mode_t mode, i2s_format_t fmt, bool is_master, uint8_t channels)=0 | ZephyrDriverCommon | pure virtual |
| beginInput(uint32_t sample_rate=48000) | SF32LB | inline |
| BG_CFG0_EN | SF32LB | static |
| BG_CFG0_EN_AMP | SF32LB | static |
| BG_CFG0_EN_RCFLT | SF32LB | static |
| BG_CFG0_EN_SMPL | SF32LB | static |
| BG_CFG0_LP_MODE | SF32LB | static |
| BG_CFG0_MIC_VREF_SEL_Msk | SF32LB | static |
| BG_CFG0_SET_VC | SF32LB | static |
| BG_CFG0_VREF_SEL_Msk | SF32LB | static |
| CFG_ADC_EN_DLY_SEL_Msk | SF32LB | static |
| CFG_ADC_ENABLE | SF32LB | static |
| CFG_DAC_ENABLE | SF32LB | static |
| clearBit(uint32_t offset, uint32_t mask) | SF32LB | inlineprotected |
| closeAnalogAdcPath() | SF32LB | inlineprotected |
| closeAnalogDacPath() | SF32LB | inlineprotected |
| configAnalogAdcPath(const AdcClockConfig &clk) | SF32LB | inlineprotected |
| configAnalogDacPath(const DacClockConfig &clk) | SF32LB | inlineprotected |
| configDacPath(bool bypass) | SF32LB | inlineprotected |
| configRxChannel(const AdcClockConfig &clk) | SF32LB | inlineprotected |
| configTxChannel(const DacClockConfig &clk) | SF32LB | inlineprotected |
| DAC_CFG_CLK_DIV_Msk | SF32LB | static |
| DAC_CFG_CLK_SRC_SEL_Msk | SF32LB | static |
| DAC_CFG_OP_MODE_Msk | SF32LB | static |
| DAC_CFG_OSR_SEL_Msk | SF32LB | static |
| DAC_CFG_PATH_RESET | SF32LB | static |
| DAC_CH_CFG_DATA_FORMAT | SF32LB | static |
| DAC_CH_CFG_DEM_MODE_Msk | SF32LB | static |
| DAC_CH_CFG_DITHER_EN | SF32LB | static |
| DAC_CH_CFG_DITHER_GAIN_Msk | SF32LB | static |
| DAC_CH_CFG_DMA_EN | SF32LB | static |
| DAC_CH_CFG_DOUT_MUTE | SF32LB | static |
| DAC_CH_CFG_ENABLE | SF32LB | static |
| DAC_CH_CFG_EXT_RAMP_EN | SF32LB | static |
| DAC_CH_CFG_EXT_RAMP_INTERVAL_Msk | SF32LB | static |
| DAC_CH_CFG_EXT_RAMP_MODE | SF32LB | static |
| DAC_CH_CFG_EXT_RAMP_STAT_Msk | SF32LB | static |
| DAC_CH_CFG_EXT_ZERO_ADJUST_EN | SF32LB | static |
| DAC_CH_CFG_FINE_VOL_Msk | SF32LB | static |
| DAC_CH_CFG_ROUGH_VOL_Msk | SF32LB | static |
| DAC_CH_CFG_SINC_GAIN_Msk | SF32LB | static |
| DAC_CH_DEBUG_BYPASS | SF32LB | static |
| DAC_CH_DEBUG_DATA_OUT_Msk | SF32LB | static |
| dacClockConfig(uint32_t sample_rate) | SF32LB | inlineprotectedstatic |
| DACx_CFG_EN_AMP | SF32LB | static |
| DACx_CFG_EN_DAC | SF32LB | static |
| DACx_CFG_EN_OS_DAC | SF32LB | static |
| DACx_CFG_EN_VCM | SF32LB | static |
| DACx_CFG_LP_MODE | SF32LB | static |
| DACx_CFG_SR | SF32LB | static |
| getInputVolume() | ZephyrDriverCommon | inlinevirtual |
| getVolume() | ZephyrDriverCommon | inlinevirtual |
| getWire() | ZephyrDriverCommon | inline |
| i2c_addr | ZephyrDriverCommon | protected |
| input_volume_percent | ZephyrDriverCommon | protected |
| isInputVolumeSupported() | ZephyrDriverCommon | inlinevirtual |
| last_fine_vol | SF32LB | protected |
| MAX_VOLUME_DB | SF32LB | static |
| MIN_VOLUME_DB | SF32LB | static |
| mute(bool mute_flag) | SF32LB | inlineprotected |
| PLL_CFG0_EN_ANA | SF32LB | static |
| PLL_CFG0_EN_IARY | SF32LB | static |
| PLL_CFG0_EN_VCO | SF32LB | static |
| PLL_CFG0_ICP_SEL_Msk | SF32LB | static |
| PLL_CFG1_C2_SEL_Msk | SF32LB | static |
| PLL_CFG1_CZ_SEL_Msk | SF32LB | static |
| PLL_CFG1_R3_SEL_Msk | SF32LB | static |
| PLL_CFG1_RZ_SEL_Msk | SF32LB | static |
| PLL_CFG2_EN_DIG | SF32LB | static |
| PLL_CFG2_RSTB | SF32LB | static |
| PLL_CFG3_EN_SDM | SF32LB | static |
| PLL_CFG4_DIVA_CLK_DAC_Msk | SF32LB | static |
| PLL_CFG4_DIVA_CLK_DIG_Msk | SF32LB | static |
| PLL_CFG4_EN_CLK_CHOP_DAC | SF32LB | static |
| PLL_CFG4_EN_CLK_DAC | SF32LB | static |
| PLL_CFG4_EN_CLK_DIG | SF32LB | static |
| PLL_CFG4_SEL_CLK_DAC | SF32LB | static |
| PLL_CFG4_SEL_CLK_DAC_SOURCE_Msk | SF32LB | static |
| PLL_CFG4_SEL_CLK_DIG | SF32LB | static |
| PLL_CFG5_EN_CLK_CHOP_BG | SF32LB | static |
| PLL_CFG5_EN_CLK_CHOP_REFGEN | SF32LB | static |
| PLL_CFG6_DIVA_CLK_ADC0_Msk | SF32LB | static |
| PLL_CFG6_DIVA_CLK_ADC1_Msk | SF32LB | static |
| PLL_CFG6_DIVA_CLK_ADC2_Msk | SF32LB | static |
| PLL_CFG6_EN_CLK_ADC0 | SF32LB | static |
| PLL_CFG6_EN_CLK_ADC1 | SF32LB | static |
| PLL_CFG6_EN_CLK_ADC2 | SF32LB | static |
| PLL_CFG6_EN_CLK_CHOP_MICBIAS | SF32LB | static |
| PLL_CFG6_SEL_CLK_ADC0 | SF32LB | static |
| PLL_CFG6_SEL_CLK_ADC1 | SF32LB | static |
| PLL_CFG6_SEL_CLK_ADC2 | SF32LB | static |
| PLL_CFG6_SEL_CLK_ADC_SOURCE | SF32LB | static |
| PLL_CFG6_SEL_CLK_CHOP_MICBIAS_Msk | SF32LB | static |
| pllAndReferencesOn() | SF32LB | inlineprotected |
| read32(uint32_t offset) | SF32LB | inlineprotected |
| readReg(uint8_t reg, uint8_t &value) | ZephyrDriverCommon | inlineprotected |
| readReg16(uint8_t reg, uint16_t &value) | ZephyrDriverCommon | inlineprotected |
| REFGEN_CFG_EN | SF32LB | static |
| REFGEN_CFG_EN_CHOP | SF32LB | static |
| REFGEN_CFG_LV_MODE | SF32LB | static |
| refgenInit() | SF32LB | inlineprotected |
| Reg enum name | SF32LB | |
| REG_ADC1_CFG1 enum value | SF32LB | |
| REG_ADC1_CFG2 enum value | SF32LB | |
| REG_ADC2_CFG1 enum value | SF32LB | |
| REG_ADC2_CFG2 enum value | SF32LB | |
| REG_ADC_ANA_CFG enum value | SF32LB | |
| REG_ADC_CFG enum value | SF32LB | |
| REG_ADC_CH0_CFG enum value | SF32LB | |
| REG_ADC_CH0_ENTRY enum value | SF32LB | |
| REG_ADC_CH1_CFG enum value | SF32LB | |
| REG_ADC_CH1_ENTRY enum value | SF32LB | |
| REG_APB_STAT enum value | SF32LB | |
| reg_base | SF32LB | protected |
| REG_BG_CFG0 enum value | SF32LB | |
| REG_BG_CFG1 enum value | SF32LB | |
| REG_BG_CFG2 enum value | SF32LB | |
| REG_CFG enum value | SF32LB | |
| REG_COMMON_CFG enum value | SF32LB | |
| REG_DAC1_CFG enum value | SF32LB | |
| REG_DAC2_CFG enum value | SF32LB | |
| REG_DAC_CFG enum value | SF32LB | |
| REG_DAC_CH0_CFG enum value | SF32LB | |
| REG_DAC_CH0_CFG_EXT enum value | SF32LB | |
| REG_DAC_CH0_DC enum value | SF32LB | |
| REG_DAC_CH0_DEBUG enum value | SF32LB | |
| REG_DAC_CH0_ENTRY enum value | SF32LB | |
| REG_DAC_CH1_CFG enum value | SF32LB | |
| REG_DAC_CH1_CFG_EXT enum value | SF32LB | |
| REG_DAC_CH1_DC enum value | SF32LB | |
| REG_DAC_CH1_DEBUG enum value | SF32LB | |
| REG_DAC_CH1_ENTRY enum value | SF32LB | |
| REG_ID enum value | SF32LB | |
| REG_IRQ enum value | SF32LB | |
| REG_IRQ_MSK enum value | SF32LB | |
| REG_PLL_CAL_CFG enum value | SF32LB | |
| REG_PLL_CAL_RESULT enum value | SF32LB | |
| REG_PLL_CFG0 enum value | SF32LB | |
| REG_PLL_CFG1 enum value | SF32LB | |
| REG_PLL_CFG2 enum value | SF32LB | |
| REG_PLL_CFG3 enum value | SF32LB | |
| REG_PLL_CFG4 enum value | SF32LB | |
| REG_PLL_CFG5 enum value | SF32LB | |
| REG_PLL_CFG6 enum value | SF32LB | |
| REG_PLL_STAT enum value | SF32LB | |
| REG_REFGEN_CFG enum value | SF32LB | |
| setActive(codec_mode_t mode) | ZephyrDriverCommon | inlinevirtual |
| setAddress(uint8_t addr) | ZephyrDriverCommon | inline |
| setBaseAddress(uintptr_t base) | SF32LB | inline |
| setBit(uint32_t offset, uint32_t mask) | SF32LB | inlineprotected |
| setDevices(input_device_t input_device, output_device_t output_device) | ZephyrDriverCommon | inlinevirtual |
| setInputVolume(int volume) | ZephyrDriverCommon | inlinevirtual |
| setMute(bool mute_flag) override | SF32LB | inlinevirtual |
| setVolume(int volume) override | SF32LB | inlinevirtual |
| setVolumeDb(int volume_db) | SF32LB | inline |
| setWire(i2c_bus_handle_t w) | ZephyrDriverCommon | inline |
| start() | SF32LB | inline |
| stop() | SF32LB | inline |
| stopInput() | SF32LB | inline |
| updateReg(uint8_t reg, uint8_t mask, uint8_t value) | ZephyrDriverCommon | inlineprotected |
| updateReg16(uint8_t reg, uint16_t mask, uint16_t value) | ZephyrDriverCommon | inlineprotected |
| updateReg32(uint32_t offset, uint32_t mask, uint32_t value) | SF32LB | inlineprotected |
| volume_percent | ZephyrDriverCommon | protected |
| wire | ZephyrDriverCommon | protected |
| write32(uint32_t offset, uint32_t value) | SF32LB | inlineprotected |
| writeReg(uint8_t reg, uint8_t value) | ZephyrDriverCommon | inlineprotected |
| writeReg16(uint8_t reg, uint16_t value) | ZephyrDriverCommon | inlineprotected |
