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arduino-audio-driver
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Header-only driver for the Nuvoton NAU8325 Class-D amplifier with DAC. More...
#include <NAU8325.h>
Public Member Functions | |
| NAU8325 (i2c_bus_handle_t wire) | |
| Constructs the driver and binds it to the given I2C bus handle. | |
| bool | begin () |
| Initializes the codec with default settings (44100 Hz, 16-bit, ratio 256) | |
| bool | begin (uint32_t fs, uint8_t bits) |
| Initializes the codec with sample rate and bit depth; uses default MCLK/FS ratio of 256. | |
| bool | begin (uint32_t fs, uint8_t bits_per_sample, uint16_t ratio) |
| Initializes the codec with explicit sample rate, bit depth, and MCLK/FS ratio. | |
| void | powerOff () |
| Powers off the analog and DAC blocks after soft-muting the output. | |
| void | powerOn () |
| Powers on the analog and DAC blocks and unmutes the output. | |
| uint16_t | readDeviceId () |
| Reads and returns the device ID register; returns 0xFFFF on failure. | |
| void | resetChip () |
| Performs a hardware reset by toggling the reset register. | |
| void | setOversampling (OversamplingMode mode) |
| Sets the DAC oversampling rate (OSR_32, OSR_64, OSR_128, or OSR_256) | |
| void | setPowerUpDefault (bool enable) |
| Enables or disables the power-up default flag in the clock detection register. | |
| void | setVolume (uint8_t left, uint8_t right) |
| Sets the DAC digital volume for left and right channels (0x00–0xFE, 0xFF = mute) | |
| void | softMute (bool enable) |
| Enables or disables soft mute on the DAC output. | |
Static Public Attributes | |
| static constexpr uint32_t | CLK_DA_AD_MAX = 6144000 |
| static constexpr uint32_t | MASTER_CLK_MAX = 49152000 |
| static constexpr uint32_t | MASTER_CLK_MIN = 2048000 |
| static const SrcAttr | mclk_n1_div [] = {{1, 0x0}, {2, 0x1}, {3, 0x2}} |
| static const SrcAttr | mclk_n2_div [] |
| static const SrcAttr | mclk_n3_mult [] |
| static constexpr uint16_t | NAU8325_ALC_ATK_MASK = (0xf << NAU8325_ALC_ATK_SFT) |
| static constexpr uint32_t | NAU8325_ALC_ATK_MAX = 0xf |
| static constexpr uint16_t | NAU8325_ALC_ATK_SFT = 8 |
| static constexpr uint16_t | NAU8325_ALC_DCY_MASK = (0xf << NAU8325_ALC_DCY_SFT) |
| static constexpr uint32_t | NAU8325_ALC_DCY_MAX = 0xf |
| static constexpr uint16_t | NAU8325_ALC_DCY_SFT = 12 |
| static constexpr uint16_t | NAU8325_ALC_EN = (0x1 << NAU8325_ALC_EN_SFT) |
| static constexpr uint16_t | NAU8325_ALC_EN_SFT = 15 |
| static constexpr uint16_t | NAU8325_ALC_HLD_MASK = (0xf << NAU8325_ALC_HLD_SFT) |
| static constexpr uint32_t | NAU8325_ALC_HLD_MAX = 0xf |
| static constexpr uint16_t | NAU8325_ALC_HLD_SFT = 4 |
| static constexpr uint16_t | NAU8325_ALC_LVL_MASK = (0xf << NAU8325_ALC_LVL_SFT) |
| static constexpr uint32_t | NAU8325_ALC_LVL_MAX = 0xf |
| static constexpr uint32_t | NAU8325_ALC_LVL_SFT = 0 |
| static constexpr uint16_t | NAU8325_ALC_MAXGAIN_MASK |
| static constexpr uint32_t | NAU8325_ALC_MAXGAIN_MAX = 7 |
| static constexpr uint16_t | NAU8325_ALC_MAXGAIN_SFT = 8 |
| static constexpr uint32_t | NAU8325_ALC_MINGAIN_MASK |
| static constexpr uint32_t | NAU8325_ALC_MINGAIN_MAX = 7 |
| static constexpr uint32_t | NAU8325_ALC_MINGAIN_SFT = 4 |
| static constexpr uint16_t | NAU8325_ANA_MUTE_MASK |
| static constexpr uint16_t | NAU8325_ANA_MUTE_SFT = 4 |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL1_CLASSD_EN = (0x3 << 12) |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL1_EN_MASK |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL1_VMID_EN = (0x3 << 0) |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL6_EN_MASK |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL6_SPKL_EN = (0x1 << 2) |
| static constexpr uint16_t | NAU8325_ANALOG_CTRL6_SPKR_EN = (0x1 << 1) |
| static constexpr uint16_t | NAU8325_ANTI_CLIP_EN |
| static constexpr uint16_t | NAU8325_ANTI_CLIP_SFT = 15 |
| static constexpr uint16_t | NAU8325_APWRUP_EN = (0x1 << NAU8325_APWRUP_SFT) |
| static constexpr uint16_t | NAU8325_APWRUP_SFT = 15 |
| static constexpr uint16_t | NAU8325_ARP_DWN_INT_MASK |
| static constexpr uint16_t | NAU8325_ARP_DWN_INT_SFT = 12 |
| static constexpr uint16_t | NAU8325_AUTO_MUTE_DIS |
| static constexpr uint16_t | NAU8325_AUTO_MUTE_SFT = 2 |
| static constexpr uint16_t | NAU8325_BIAS_VMID_SEL_MASK |
| static constexpr uint16_t | NAU8325_BIAS_VMID_SEL_SFT = 4 |
| static constexpr uint16_t | NAU8325_BIASEN_MASK = (0x3 << NAU8325_BIASEN_SFT) |
| static constexpr uint16_t | NAU8325_BIASEN_SFT = 2 |
| static constexpr uint16_t | NAU8325_CLASSD_COARSE_GAIN_MASK = 0x7 |
| static constexpr uint16_t | NAU8325_CLASSD_FINE_MASK |
| static constexpr uint16_t | NAU8325_CLASSD_FINE_SFT = 3 |
| static constexpr uint16_t | NAU8325_CLASSD_OCPN_MASK |
| static constexpr uint16_t | NAU8325_CLASSD_OCPN_SFT = 8 |
| static constexpr uint16_t | NAU8325_CLASSD_OCPP_MASK |
| static constexpr uint16_t | NAU8325_CLASSD_OCPP_SFT = 4 |
| static constexpr uint16_t | NAU8325_CLASSD_SLEWN_MASK = 0xf |
| static constexpr uint16_t | NAU8325_CLASSDEN_MASK |
| static constexpr uint16_t | NAU8325_CLASSDEN_SFT = 12 |
| static constexpr uint16_t | NAU8325_CLIP_INT_DIS |
| static constexpr uint16_t | NAU8325_CLIP_INT_DIS_SFT = 3 |
| static constexpr uint16_t | NAU8325_CLIP_INT_MASK |
| static constexpr uint16_t | NAU8325_CLIP_INT_SFT = 11 |
| static constexpr uint16_t | NAU8325_CLIP_MASK = (0x1 << 7) |
| static constexpr uint32_t | NAU8325_CLK_DAC_DELAY_EN |
| static constexpr uint32_t | NAU8325_CLK_DAC_DELAY_SFT = 4 |
| static constexpr uint32_t | NAU8325_CLK_DAC_SRC_MASK |
| static constexpr uint32_t | NAU8325_CLK_DAC_SRC_SFT = 12 |
| static constexpr uint32_t | NAU8325_CLK_MUL_SRC_MASK |
| static constexpr uint32_t | NAU8325_CLK_MUL_SRC_SFT = 6 |
| static constexpr uint32_t | NAU8325_CLKPWRUP_DIS |
| static constexpr uint32_t | NAU8325_CLKPWRUP_SFT = 14 |
| static constexpr uint16_t | NAU8325_CMB8_0_MASK = (0x1 << NAU8325_CMB8_0_SFT) |
| static constexpr uint16_t | NAU8325_CMB8_0_SFT = 13 |
| static constexpr uint16_t | NAU8325_DAC_HPF_APP_MASK |
| static constexpr uint16_t | NAU8325_DAC_HPF_APP_SFT = 4 |
| static constexpr uint16_t | NAU8325_DAC_HPF_EN = (0x1 << NAU8325_DAC_HPF_SFT) |
| static constexpr uint16_t | NAU8325_DAC_HPF_FCUT_MASK |
| static constexpr uint32_t | NAU8325_DAC_HPF_FCUT_SFT = 0 |
| static constexpr uint16_t | NAU8325_DAC_HPF_SFT = 15 |
| static constexpr uint16_t | NAU8325_DAC_LEFT_CH_EN |
| static constexpr uint16_t | NAU8325_DAC_LEFT_CH_EN_SFT = 3 |
| static constexpr uint16_t | NAU8325_DAC_LEFT_SFT = 6 |
| static constexpr uint16_t | NAU8325_DAC_OVERSAMPLE_128 |
| static constexpr uint16_t | NAU8325_DAC_OVERSAMPLE_256 |
| static constexpr uint16_t | NAU8325_DAC_OVERSAMPLE_32 |
| static constexpr uint16_t | NAU8325_DAC_OVERSAMPLE_64 |
| static constexpr uint16_t | NAU8325_DAC_OVERSAMPLE_MASK |
| static constexpr uint32_t | NAU8325_DAC_OVERSAMPLE_SFT = 0 |
| static constexpr uint16_t | NAU8325_DAC_RIGHT_CH_EN |
| static constexpr uint16_t | NAU8325_DAC_RIGHT_CH_EN_SFT = 2 |
| static constexpr uint16_t | NAU8325_DAC_RIGHT_MASK |
| static constexpr uint16_t | NAU8325_DAC_RIGHT_SFT = 3 |
| static constexpr uint32_t | NAU8325_DAC_VOL_MAX = 0xfe |
| static constexpr uint16_t | NAU8325_DAC_VOLUME_L_EN |
| static constexpr uint16_t | NAU8325_DAC_VOLUME_L_SFT = 8 |
| static constexpr uint16_t | NAU8325_DAC_VOLUME_R_EN |
| static constexpr uint32_t | NAU8325_DAC_VOLUME_R_SFT = 0 |
| static constexpr uint16_t | NAU8325_DAC_ZC_EN = (0x1 << NAU8325_DAC_ZC_SFT) |
| static constexpr uint16_t | NAU8325_DAC_ZC_SFT = 8 |
| static constexpr uint32_t | NAU8325_DACCLKEN_MASK |
| static constexpr uint32_t | NAU8325_DACCLKEN_R_MASK |
| static constexpr uint32_t | NAU8325_DACCLKEN_R_SFT = 10 |
| static constexpr uint32_t | NAU8325_DACCLKEN_SFT = 6 |
| static constexpr uint16_t | NAU8325_DACCM_CTL_MASK |
| static constexpr uint16_t | NAU8325_DACCM_CTL_SFT = 14 |
| static constexpr uint16_t | NAU8325_DACEN_MASK = (0x3 << NAU8325_DACEN_SFT) |
| static constexpr uint16_t | NAU8325_DACEN_R_MASK = (0x3 << NAU8325_DACEN_R_SFT) |
| static constexpr uint16_t | NAU8325_DACEN_R_SFT = 8 |
| static constexpr uint16_t | NAU8325_DACEN_SFT = 4 |
| static constexpr uint16_t | NAU8325_DACREFCAP_MASK |
| static constexpr uint16_t | NAU8325_DACREFCAP_SFT = 6 |
| static constexpr uint16_t | NAU8325_DACTEST_MASK = (0x7 << NAU8325_DACTEST_SFT) |
| static constexpr uint16_t | NAU8325_DACTEST_SFT = 8 |
| static constexpr uint16_t | NAU8325_DACVREFSEL_MASK |
| static constexpr uint16_t | NAU8325_DACVREFSEL_SFT = 2 |
| static constexpr uint16_t | NAU8325_DEM_DITH_EN = (0x1 << NAU8325_DEM_DITH_SFT) |
| static constexpr uint16_t | NAU8325_DEM_DITH_SFT = 13 |
| static constexpr uint16_t | NAU8325_ENA_CTRL_DAC_EN_MASK = 0x000C |
| static constexpr uint16_t | NAU8325_ENA_CTRL_DACL_EN = 0x0004 |
| static constexpr uint16_t | NAU8325_ENA_CTRL_DACR_EN = 0x0008 |
| static constexpr uint16_t | NAU8325_GAINZI2_MASK = 0x7 |
| static constexpr uint16_t | NAU8325_GAINZI3_MASK = (0x1 << NAU8325_GAINZI3_SFT) |
| static constexpr uint16_t | NAU8325_GAINZI3_SFT = 4 |
| static constexpr uint16_t | NAU8325_I2C_ADDR = 0x21 |
| static constexpr uint16_t | NAU8325_I2S_BP_INV = (0x1 << NAU8325_I2S_BP_SFT) |
| static constexpr uint16_t | NAU8325_I2S_BP_MASK = (0x1 << NAU8325_I2S_BP_SFT) |
| static constexpr uint16_t | NAU8325_I2S_BP_SFT = 7 |
| static constexpr uint16_t | NAU8325_I2S_DACPSHS0_MASK |
| static constexpr uint16_t | NAU8325_I2S_DACPSHS0_SFT = 4 |
| static constexpr uint16_t | NAU8325_I2S_DF_I2S = 0x2 |
| static constexpr uint16_t | NAU8325_I2S_DF_LEFT = 0x1 |
| static constexpr uint16_t | NAU8325_I2S_DF_MASK = 0x3 |
| static constexpr uint16_t | NAU8325_I2S_DF_PCM_AB = 0x3 |
| static constexpr uint16_t | NAU8325_I2S_DF_RIGTH = 0x0 |
| static constexpr uint16_t | NAU8325_I2S_DL_16 = (0x0 << NAU8325_I2S_DL_SFT) |
| static constexpr uint16_t | NAU8325_I2S_DL_20 = (0x1 << NAU8325_I2S_DL_SFT) |
| static constexpr uint16_t | NAU8325_I2S_DL_24 = (0x2 << NAU8325_I2S_DL_SFT) |
| static constexpr uint16_t | NAU8325_I2S_DL_32 = (0x3 << NAU8325_I2S_DL_SFT) |
| static constexpr uint16_t | NAU8325_I2S_DL_MASK = (0x3 << NAU8325_I2S_DL_SFT) |
| static constexpr uint16_t | NAU8325_I2S_DL_SFT = 2 |
| static constexpr uint16_t | NAU8325_I2S_PCMB_EN = (0x1 << NAU8325_I2S_PCMB_SFT) |
| static constexpr uint16_t | NAU8325_I2S_PCMB_SFT = 6 |
| static constexpr uint16_t | NAU8325_INT_STATUS_MASK = 0x7f |
| static constexpr uint16_t | NAU8325_IRQ_DS_HIGH = (0x1 << NAU8325_IRQ_DS_SFT) |
| static constexpr uint16_t | NAU8325_IRQ_DS_SFT = 4 |
| static constexpr uint16_t | NAU8325_IRQ_OUTPUT_EN |
| static constexpr uint16_t | NAU8325_IRQ_OUTPUT_SFT = 3 |
| static constexpr uint16_t | NAU8325_IRQ_PE_EN = (0x1 << NAU8325_IRQ_PE_SFT) |
| static constexpr uint16_t | NAU8325_IRQ_PE_SFT = 5 |
| static constexpr uint16_t | NAU8325_IRQ_PIN_DEBUG_EN |
| static constexpr uint16_t | NAU8325_IRQ_PIN_DEBUG_SFT = 2 |
| static constexpr uint16_t | NAU8325_IRQ_PL_ACT_HIGH |
| static constexpr uint16_t | NAU8325_IRQ_PL_SFT = 7 |
| static constexpr uint16_t | NAU8325_IRQ_PS_SFT = 6 |
| static constexpr uint16_t | NAU8325_IRQ_PS_UP = (0x1 << NAU8325_IRQ_PS_SFT) |
| static constexpr uint16_t | NAU8325_IRQOUT_SEL_MASK |
| static constexpr uint16_t | NAU8325_IRQOUT_SEL_SEF = 14 |
| static constexpr uint16_t | NAU8325_L_CHANNEL_Vol_MASK = 0x1f |
| static constexpr uint16_t | NAU8325_LPF_IN1_EN |
| static constexpr uint16_t | NAU8325_LPF_IN1_EN_SFT = 15 |
| static constexpr uint16_t | NAU8325_LPF_IN1_TC_MASK |
| static constexpr uint16_t | NAU8325_LPF_IN1_TC_SFT = 12 |
| static constexpr uint16_t | NAU8325_LPF_IN2_EN |
| static constexpr uint16_t | NAU8325_LPF_IN2_EN_SFT = 11 |
| static constexpr uint16_t | NAU8325_LPF_IN2_TC_MASK |
| static constexpr uint16_t | NAU8325_LPF_IN2_TC_SFT = 8 |
| static constexpr uint16_t | NAU8325_LVD_INT_DIS |
| static constexpr uint16_t | NAU8325_LVD_INT_DIS_SFT = 2 |
| static constexpr uint16_t | NAU8325_LVD_INT_MASK = (0x1 << NAU8325_LVD_INT_SFT) |
| static constexpr uint16_t | NAU8325_LVD_INT_SFT = 10 |
| static constexpr uint32_t | NAU8325_MCLK4XEN_EN = (0x1 << 3) |
| static constexpr uint32_t | NAU8325_MCLK8XEN_EN = (0x1 << NAU8325_MCLK8XEN_SFT) |
| static constexpr uint32_t | NAU8325_MCLK8XEN_SFT = 4 |
| static constexpr uint32_t | NAU8325_MCLK_RANGE_EN |
| static constexpr uint32_t | NAU8325_MCLK_RANGE_SFT = 15 |
| static constexpr uint32_t | NAU8325_MCLK_SEL_MASK |
| static constexpr uint32_t | NAU8325_MCLK_SEL_SFT = 3 |
| static constexpr uint32_t | NAU8325_MCLK_SRC_MASK = 0x7 |
| static constexpr uint16_t | NAU8325_MIPS500_MASK = (0x1 << 6) |
| static constexpr uint16_t | NAU8325_MUTEB_MASK = (0x1 << 3) |
| static constexpr uint16_t | NAU8325_NAU8325_DAC_LEFT_MASK |
| static constexpr uint16_t | NAU8325_OCP_OTP_SHTDWN_INT_MASK |
| static constexpr uint16_t | NAU8325_OCP_OTP_SHTDWN_INT_SFT = 4 |
| static constexpr uint16_t | NAU8325_OSR100_MASK = (0x1 << 7) |
| static constexpr uint16_t | NAU8325_PCM8BIT0_MASK |
| static constexpr uint16_t | NAU8325_PCM8BIT0_SFT = 8 |
| static constexpr uint16_t | NAU8325_PCM_OFFSET_CTRL_EN |
| static constexpr uint16_t | NAU8325_PCM_OFFSET_CTRL_SFT = 14 |
| static constexpr uint16_t | NAU8325_PCM_TS_EN = (0x1 << NAU8325_PCM_TS_SFT) |
| static constexpr uint16_t | NAU8325_PCM_TS_SFT = 10 |
| static constexpr uint16_t | NAU8325_PDM_LCH_EDGE__MASK |
| static constexpr uint16_t | NAU8325_PDM_LCH_EDGE_SFT = 1 |
| static constexpr uint16_t | NAU8325_PDM_MODE_EN = 0x1 |
| static constexpr uint16_t | NAU8325_PDOSCB_MASK = (0x1 << 2) |
| static constexpr uint16_t | NAU8325_PGAL_GAIN_MASK = (0x1f << 8) |
| static constexpr uint16_t | NAU8325_POWER_DOWN_L_MASK |
| static constexpr uint16_t | NAU8325_POWER_DOWN_L_SFT = 8 |
| static constexpr uint16_t | NAU8325_POWER_DOWN_R_MASK |
| static constexpr uint16_t | NAU8325_POWER_DOWN_R_SFT = 6 |
| static constexpr uint16_t | NAU8325_POWERDOWN1B_D_MASK = (0x1 << 1) |
| static constexpr uint16_t | NAU8325_PWMMOD_MASK = (0x3 << NAU8325_PWMMOD_SFT) |
| static constexpr uint16_t | NAU8325_PWMMOD_SFT = 14 |
| static constexpr uint16_t | NAU8325_PWR_INT_DIS |
| static constexpr uint16_t | NAU8325_PWR_INT_DIS_SFT = 8 |
| static constexpr uint16_t | NAU8325_PWR_INT_MASK = 0x1 |
| static constexpr uint16_t | NAU8325_PWRUP_DFT = (0x1 << NAU8325_PWRUP_DFT_SFT) |
| static constexpr uint16_t | NAU8325_PWRUP_DFT_SFT = 13 |
| static constexpr uint16_t | NAU8325_R00_HARDWARE_RST = 0x00 |
| static constexpr uint16_t | NAU8325_R01_SOFTWARE_RST = 0x01 |
| static constexpr uint16_t | NAU8325_R02_DEVICE_ID = 0x02 |
| static constexpr uint32_t | NAU8325_R03_CLK_CTRL = 0x03 |
| static constexpr uint16_t | NAU8325_R04_ENA_CTRL = 0x04 |
| static constexpr uint16_t | NAU8325_R05_INTERRUPT_CTRL = 0x05 |
| static constexpr uint16_t | NAU8325_R06_INT_CLR_STATUS = 0x06 |
| static constexpr uint16_t | NAU8325_R09_IRQOUT = 0x09 |
| static constexpr uint16_t | NAU8325_R0A_IO_CTRL = 0x0a |
| static constexpr uint16_t | NAU8325_R0B_PDM_CTRL = 0x0b |
| static constexpr uint16_t | NAU8325_R0C_TDM_CTRL = 0x0c |
| static constexpr uint16_t | NAU8325_R0D_I2S_PCM_CTRL1 = 0x0d |
| static constexpr uint16_t | NAU8325_R0E_I2S_PCM_CTRL2 = 0x0e |
| static constexpr uint16_t | NAU8325_R0F_L_TIME_SLOT = 0x0f |
| static constexpr uint16_t | NAU8325_R10_R_TIME_SLOT = 0x10 |
| static constexpr uint16_t | NAU8325_R11_HPF_CTRL = 0x11 |
| static constexpr uint16_t | NAU8325_R12_MUTE_CTRL = 0x12 |
| static constexpr uint16_t | NAU8325_R13_DAC_VOLUME = 0x13 |
| static constexpr uint16_t | NAU8325_R1D_DEBUG_READ1 = 0x1d |
| static constexpr uint16_t | NAU8325_R1F_DEBUG_READ2 = 0x1f |
| static constexpr uint16_t | NAU8325_R22_DEBUG_READ3 = 0x22 |
| static constexpr uint16_t | NAU8325_R29_DAC_CTRL1 = 0x29 |
| static constexpr uint16_t | NAU8325_R2A_DAC_CTRL2 = 0x2a |
| static constexpr uint16_t | NAU8325_R2C_ALC_CTRL1 = 0x2c |
| static constexpr uint16_t | NAU8325_R2D_ALC_CTRL2 = 0x2d |
| static constexpr uint16_t | NAU8325_R2E_ALC_CTRL3 = 0x2e |
| static constexpr uint16_t | NAU8325_R2F_ALC_CTRL4 = 0x2f |
| static constexpr uint32_t | NAU8325_R40_CLK_DET_CTRL = 0x40 |
| static constexpr uint16_t | NAU8325_R49_TEST_STATUS = 0x49 |
| static constexpr uint16_t | NAU8325_R4A_ANALOG_READ = 0x4a |
| static constexpr uint16_t | NAU8325_R50_MIXER_CTRL = 0x50 |
| static constexpr uint16_t | NAU8325_R55_MISC_CTRL = 0x55 |
| static constexpr uint16_t | NAU8325_R60_BIAS_ADJ = 0x60 |
| static constexpr uint16_t | NAU8325_R61_ANALOG_CONTROL_1 = 0x61 |
| static constexpr uint16_t | NAU8325_R62_ANALOG_CONTROL_2 = 0x62 |
| static constexpr uint16_t | NAU8325_R63_ANALOG_CONTROL_3 = 0x63 |
| static constexpr uint16_t | NAU8325_R64_ANALOG_CONTROL_4 = 0x64 |
| static constexpr uint16_t | NAU8325_R65_ANALOG_CONTROL_5 = 0x65 |
| static constexpr uint16_t | NAU8325_R66_ANALOG_CONTROL_6 = 0x66 |
| static constexpr uint16_t | NAU8325_R69_CLIP_CTRL = 0x69 |
| static constexpr uint16_t | NAU8325_R73_RDAC = 0x73 |
| static constexpr uint16_t | NAU8325_R_CHANNEL_Vol_MASK |
| static constexpr uint16_t | NAU8325_R_CHANNEL_Vol_SFT = 8 |
| static constexpr uint32_t | NAU8325_REG_ADDR_LEN = 16 |
| static constexpr uint16_t | NAU8325_REG_ALT_SRATE_EN |
| static constexpr uint16_t | NAU8325_REG_ALT_SRATE_SFT = 9 |
| static constexpr uint32_t | NAU8325_REG_DATA_LEN = 16 |
| static constexpr uint32_t | NAU8325_REG_DIV_MAX = (0x1 << 8) |
| static constexpr uint32_t | NAU8325_REG_MAX = NAU8325_R73_RDAC |
| static constexpr uint16_t | NAU8325_REG_SRATE_MASK |
| static constexpr uint16_t | NAU8325_REG_SRATE_SFT = 10 |
| static constexpr uint16_t | NAU8325_SCAN_MODE_MASK = (0x1 << 6) |
| static constexpr uint16_t | NAU8325_SDB_MASK = (0x1 << 5) |
| static constexpr uint16_t | NAU8325_SHORT_FS_DET_DIS |
| static constexpr uint16_t | NAU8325_SHORT_FS_DET_SFT = 9 |
| static constexpr uint16_t | NAU8325_SHORTL_MASK = (0x1 << 2) |
| static constexpr uint16_t | NAU8325_SHORTR_MASK = (0x1 << 3) |
| static constexpr uint16_t | NAU8325_SHUTDWNDRVR_L_MASK = (0x1 << 4) |
| static constexpr uint16_t | NAU8325_SHUTDWNDRVR_R_MASK = (0x1 << 5) |
| static constexpr uint16_t | NAU8325_SOFT_MUTE = (0x1 << NAU8325_SOFT_MUTE_SFT) |
| static constexpr uint16_t | NAU8325_SOFT_MUTE_SFT = 9 |
| static constexpr uint16_t | NAU8325_TALARM_MASK = (0x1 << 4) |
| static constexpr uint16_t | NAU8325_TDM_EN = (0x1 << NAU8325_TDM_SFT) |
| static constexpr uint16_t | NAU8325_TDM_SFT = 15 |
| static constexpr uint16_t | NAU8325_TEMP_COMP_ACT2_MASK = (0x1 << 5) |
| static constexpr uint16_t | NAU8325_TMDET_MASK = 0x3 |
| static constexpr uint16_t | NAU8325_TSLOT_L0_MASK = 0x1ff |
| static constexpr uint16_t | NAU8325_TSLOT_R0_MASK = 0x1ff |
| static constexpr uint16_t | NAU8325_UA_OFFSET_MASK |
| static constexpr uint16_t | NAU8325_UA_OFFSET_SFT = 12 |
| static constexpr uint16_t | NAU8325_UNMUTE_CTL_MASK |
| static constexpr uint16_t | NAU8325_UNMUTE_CTL_SFT = 6 |
| static constexpr uint16_t | NAU8325_VBATLOW_MASK = (0x3 << NAU8325_VBATLOW_SFT) |
| static constexpr uint16_t | NAU8325_VBATLOW_SFT = 14 |
| static constexpr uint16_t | NAU8325_VDDSPK_LIM_EN |
| static constexpr uint16_t | NAU8325_VDDSPK_LIM_MASK = (0x7 << 9) |
| static constexpr uint16_t | NAU8325_VDDSPK_LIM_SFT = 8 |
| static constexpr uint16_t | NAU8325_VMDFSTENB_MASK |
| static constexpr uint16_t | NAU8325_VMDFSTENB_SFT = 14 |
| static constexpr uint16_t | NAU8325_VMIDEN_MASK = 0x3 |
| static constexpr uint16_t | NAU8325_VMIDEN_SFT = 0x03 |
| static const OsrAttr | osr_dac_sel [] |
| static const RegDefault | reg_defaults [] |
| static const SRateAttr | target_srate_table [] |
Header-only driver for the Nuvoton NAU8325 Class-D amplifier with DAC.
The NAU8325 is an I2C-controlled mono Class-D amplifier with an integrated 16/20/24/32-bit DAC. This driver configures the clock tree (MCLK → N1/N2/N3 dividers → DAC clock), I2S format, oversampling rate, ALC, and analog bias registers. All configuration state is held per-instance, so multiple devices on the same bus are supported.
Typical usage:
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Constructs the driver and binds it to the given I2C bus handle.
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Initializes the codec with default settings (44100 Hz, 16-bit, ratio 256)
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Initializes the codec with sample rate and bit depth; uses default MCLK/FS ratio of 256.
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Initializes the codec with explicit sample rate, bit depth, and MCLK/FS ratio.
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Powers off the analog and DAC blocks after soft-muting the output.
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Powers on the analog and DAC blocks and unmutes the output.
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Reads and returns the device ID register; returns 0xFFFF on failure.
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Performs a hardware reset by toggling the reset register.
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Sets the DAC oversampling rate (OSR_32, OSR_64, OSR_128, or OSR_256)
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Enables or disables the power-up default flag in the clock detection register.
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Sets the DAC digital volume for left and right channels (0x00–0xFE, 0xFF = mute)
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Enables or disables soft mute on the DAC output.
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