arduino-audio-driver
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NAU8325.h
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1#pragma once
2
3#include "DriverCommon.h"
4#include "Platforms/API_I2C.h"
5#include "Platforms/Logger.h"
6#include "stdint.h"
7
8namespace audio_driver {
9
10struct SrcAttr {
11 int param;
12 uint8_t val;
13};
14
15struct OsrAttr {
16 int osr;
17 uint8_t clk_src;
18};
19
20struct SRateAttr {
21 int fs;
22 uint8_t range;
23 bool max;
24 uint32_t mclk_src[3];
25};
26
27struct RegDefault {
28 uint16_t reg;
29 uint16_t val;
30};
31
32enum AudioI2SFormat { I2S_STD, LEFT_JUSTIFIED, RIGHT_JUSTIFIED, DSP_A, DSP_B };
33enum ClockPolarity { NORMAL_BCLK, INVERTED_BCLK };
34enum OversamplingMode { OSR_64 = 2, OSR_128 = 1, OSR_256 = 0, OSR_32 = 4 };
35
42
43
63class NAU8325 {
64 public:
65 static constexpr uint16_t NAU8325_I2C_ADDR = 0x21;
66 static constexpr uint16_t NAU8325_R00_HARDWARE_RST = 0x00;
67 static constexpr uint16_t NAU8325_R01_SOFTWARE_RST = 0x01;
68 static constexpr uint16_t NAU8325_R02_DEVICE_ID = 0x02;
69 static constexpr uint32_t NAU8325_R03_CLK_CTRL = 0x03;
70 static constexpr uint16_t NAU8325_R04_ENA_CTRL = 0x04;
71 static constexpr uint16_t NAU8325_R05_INTERRUPT_CTRL = 0x05;
72 static constexpr uint16_t NAU8325_R06_INT_CLR_STATUS = 0x06;
73 static constexpr uint16_t NAU8325_R09_IRQOUT = 0x09;
74 static constexpr uint16_t NAU8325_R0A_IO_CTRL = 0x0a;
75 static constexpr uint16_t NAU8325_R0B_PDM_CTRL = 0x0b;
76 static constexpr uint16_t NAU8325_R0C_TDM_CTRL = 0x0c;
77 static constexpr uint16_t NAU8325_R0D_I2S_PCM_CTRL1 = 0x0d;
78 static constexpr uint16_t NAU8325_R0E_I2S_PCM_CTRL2 = 0x0e;
79 static constexpr uint16_t NAU8325_R0F_L_TIME_SLOT = 0x0f;
80 static constexpr uint16_t NAU8325_R10_R_TIME_SLOT = 0x10;
81 static constexpr uint16_t NAU8325_R11_HPF_CTRL = 0x11;
82 static constexpr uint16_t NAU8325_R12_MUTE_CTRL = 0x12;
83 static constexpr uint16_t NAU8325_R13_DAC_VOLUME = 0x13;
84 static constexpr uint16_t NAU8325_R1D_DEBUG_READ1 = 0x1d;
85 static constexpr uint16_t NAU8325_R1F_DEBUG_READ2 = 0x1f;
86 static constexpr uint16_t NAU8325_R22_DEBUG_READ3 = 0x22;
87 static constexpr uint16_t NAU8325_R29_DAC_CTRL1 = 0x29;
88 static constexpr uint16_t NAU8325_R2A_DAC_CTRL2 = 0x2a;
89 static constexpr uint16_t NAU8325_R2C_ALC_CTRL1 = 0x2c;
90 static constexpr uint16_t NAU8325_R2D_ALC_CTRL2 = 0x2d;
91 static constexpr uint16_t NAU8325_R2E_ALC_CTRL3 = 0x2e;
92 static constexpr uint16_t NAU8325_R2F_ALC_CTRL4 = 0x2f;
93 static constexpr uint32_t NAU8325_R40_CLK_DET_CTRL = 0x40;
94 static constexpr uint16_t NAU8325_R49_TEST_STATUS = 0x49;
95 static constexpr uint16_t NAU8325_R4A_ANALOG_READ = 0x4a;
96 static constexpr uint16_t NAU8325_R50_MIXER_CTRL = 0x50;
97 static constexpr uint16_t NAU8325_R55_MISC_CTRL = 0x55;
98 static constexpr uint16_t NAU8325_R60_BIAS_ADJ = 0x60;
99 static constexpr uint16_t NAU8325_R61_ANALOG_CONTROL_1 = 0x61;
100 static constexpr uint16_t NAU8325_R62_ANALOG_CONTROL_2 = 0x62;
101 static constexpr uint16_t NAU8325_R63_ANALOG_CONTROL_3 = 0x63;
102 static constexpr uint16_t NAU8325_R64_ANALOG_CONTROL_4 = 0x64;
103 static constexpr uint16_t NAU8325_R65_ANALOG_CONTROL_5 = 0x65;
104 static constexpr uint16_t NAU8325_R66_ANALOG_CONTROL_6 = 0x66;
105 static constexpr uint16_t NAU8325_R69_CLIP_CTRL = 0x69;
106 static constexpr uint16_t NAU8325_R73_RDAC = 0x73;
107 static constexpr uint32_t NAU8325_REG_MAX = NAU8325_R73_RDAC;
108 static constexpr uint16_t NAU8325_VMIDEN_SFT = 0x03;
109 static constexpr uint32_t NAU8325_REG_ADDR_LEN = 16;
110 static constexpr uint32_t NAU8325_REG_DATA_LEN = 16;
111 static constexpr uint32_t NAU8325_CLK_DAC_SRC_SFT = 12;
112 static constexpr uint32_t NAU8325_CLK_DAC_SRC_MASK =
113 (0x3 << NAU8325_CLK_DAC_SRC_SFT);
114 static constexpr uint32_t NAU8325_CLK_MUL_SRC_SFT = 6;
115 static constexpr uint32_t NAU8325_CLK_MUL_SRC_MASK =
116 (0x3 << NAU8325_CLK_MUL_SRC_SFT);
117 static constexpr uint32_t NAU8325_MCLK_SEL_SFT = 3;
118 static constexpr uint32_t NAU8325_MCLK_SEL_MASK =
119 (0x7 << NAU8325_MCLK_SEL_SFT);
120 static constexpr uint32_t NAU8325_MCLK_SRC_MASK = 0x7;
121 static constexpr uint16_t NAU8325_DAC_LEFT_CH_EN_SFT = 3;
122 static constexpr uint16_t NAU8325_DAC_LEFT_CH_EN =
123 (0x1 << NAU8325_DAC_LEFT_CH_EN_SFT);
124 static constexpr uint16_t NAU8325_DAC_RIGHT_CH_EN_SFT = 2;
125 static constexpr uint16_t NAU8325_DAC_RIGHT_CH_EN =
126 (0x1 << NAU8325_DAC_RIGHT_CH_EN_SFT);
127 static constexpr uint16_t NAU8325_ENA_CTRL_DACR_EN = 0x0008;
128 static constexpr uint16_t NAU8325_ENA_CTRL_DACL_EN = 0x0004;
129 static constexpr uint16_t NAU8325_ENA_CTRL_DAC_EN_MASK = 0x000C;
130 static constexpr uint16_t NAU8325_ARP_DWN_INT_SFT = 12;
131 static constexpr uint16_t NAU8325_ARP_DWN_INT_MASK =
132 (0x1 << NAU8325_ARP_DWN_INT_SFT);
133 static constexpr uint16_t NAU8325_CLIP_INT_SFT = 11;
134 static constexpr uint16_t NAU8325_CLIP_INT_MASK =
135 (0x1 << NAU8325_CLIP_INT_SFT);
136 static constexpr uint16_t NAU8325_LVD_INT_SFT = 10;
137 static constexpr uint16_t NAU8325_LVD_INT_MASK = (0x1 << NAU8325_LVD_INT_SFT);
138 static constexpr uint16_t NAU8325_PWR_INT_DIS_SFT = 8;
139 static constexpr uint16_t NAU8325_PWR_INT_DIS =
140 (0x1 << NAU8325_PWR_INT_DIS_SFT);
141 static constexpr uint16_t NAU8325_OCP_OTP_SHTDWN_INT_SFT = 4;
142 static constexpr uint16_t NAU8325_OCP_OTP_SHTDWN_INT_MASK =
143 (0x1 << NAU8325_OCP_OTP_SHTDWN_INT_SFT);
144 static constexpr uint16_t NAU8325_CLIP_INT_DIS_SFT = 3;
145 static constexpr uint16_t NAU8325_CLIP_INT_DIS =
146 (0x1 << NAU8325_CLIP_INT_DIS_SFT);
147 static constexpr uint16_t NAU8325_LVD_INT_DIS_SFT = 2;
148 static constexpr uint16_t NAU8325_LVD_INT_DIS =
149 (0x1 << NAU8325_LVD_INT_DIS_SFT);
150 static constexpr uint16_t NAU8325_PWR_INT_MASK = 0x1;
151 static constexpr uint16_t NAU8325_INT_STATUS_MASK = 0x7f;
152 static constexpr uint16_t NAU8325_IRQOUT_SEL_SEF = 14;
153 static constexpr uint16_t NAU8325_IRQOUT_SEL_MASK =
154 (0x3 << NAU8325_IRQOUT_SEL_SEF);
155 static constexpr uint16_t NAU8325_DEM_DITH_SFT = 13;
156 static constexpr uint16_t NAU8325_DEM_DITH_EN = (0x1 << NAU8325_DEM_DITH_SFT);
157 static constexpr uint16_t NAU8325_GAINZI3_SFT = 4;
158 static constexpr uint16_t NAU8325_GAINZI3_MASK = (0x1 << NAU8325_GAINZI3_SFT);
159 static constexpr uint16_t NAU8325_GAINZI2_MASK = 0x7;
160 static constexpr uint16_t NAU8325_IRQ_PL_SFT = 7;
161 static constexpr uint16_t NAU8325_IRQ_PL_ACT_HIGH =
162 (0x1 << NAU8325_IRQ_PL_SFT);
163 static constexpr uint16_t NAU8325_IRQ_PS_SFT = 6;
164 static constexpr uint16_t NAU8325_IRQ_PS_UP = (0x1 << NAU8325_IRQ_PS_SFT);
165 static constexpr uint16_t NAU8325_IRQ_PE_SFT = 5;
166 static constexpr uint16_t NAU8325_IRQ_PE_EN = (0x1 << NAU8325_IRQ_PE_SFT);
167 static constexpr uint16_t NAU8325_IRQ_DS_SFT = 4;
168 static constexpr uint16_t NAU8325_IRQ_DS_HIGH = (0x1 << NAU8325_IRQ_DS_SFT);
169 static constexpr uint16_t NAU8325_IRQ_OUTPUT_SFT = 3;
170 static constexpr uint16_t NAU8325_IRQ_OUTPUT_EN =
171 (0x1 << NAU8325_IRQ_OUTPUT_SFT);
172 static constexpr uint16_t NAU8325_IRQ_PIN_DEBUG_SFT = 2;
173 static constexpr uint16_t NAU8325_IRQ_PIN_DEBUG_EN =
174 (0x1 << NAU8325_IRQ_PIN_DEBUG_SFT);
175 static constexpr uint16_t NAU8325_PDM_LCH_EDGE_SFT = 1;
176 static constexpr uint16_t NAU8325_PDM_LCH_EDGE__MASK =
177 (0x1 << NAU8325_PDM_LCH_EDGE_SFT);
178 static constexpr uint16_t NAU8325_PDM_MODE_EN = 0x1;
179 static constexpr uint16_t NAU8325_TDM_SFT = 15;
180 static constexpr uint16_t NAU8325_TDM_EN = (0x1 << NAU8325_TDM_SFT);
181 static constexpr uint16_t NAU8325_PCM_OFFSET_CTRL_SFT = 14;
182 static constexpr uint16_t NAU8325_PCM_OFFSET_CTRL_EN =
183 (0x1 << NAU8325_PCM_OFFSET_CTRL_SFT);
184 static constexpr uint16_t NAU8325_DAC_LEFT_SFT = 6;
185 static constexpr uint16_t NAU8325_NAU8325_DAC_LEFT_MASK =
186 (0x7 << NAU8325_DAC_LEFT_SFT);
187 static constexpr uint16_t NAU8325_DAC_RIGHT_SFT = 3;
188 static constexpr uint16_t NAU8325_DAC_RIGHT_MASK =
189 (0x7 << NAU8325_DAC_RIGHT_SFT);
190 static constexpr uint16_t NAU8325_DACCM_CTL_SFT = 14;
191 static constexpr uint16_t NAU8325_DACCM_CTL_MASK =
192 (0x3 << NAU8325_DACCM_CTL_SFT);
193 static constexpr uint16_t NAU8325_CMB8_0_SFT = 13;
194 static constexpr uint16_t NAU8325_CMB8_0_MASK = (0x1 << NAU8325_CMB8_0_SFT);
195 static constexpr uint16_t NAU8325_UA_OFFSET_SFT = 12;
196 static constexpr uint16_t NAU8325_UA_OFFSET_MASK =
197 (0x1 << NAU8325_UA_OFFSET_SFT);
198 static constexpr uint16_t NAU8325_I2S_BP_SFT = 7;
199 static constexpr uint16_t NAU8325_I2S_BP_MASK = (0x1 << NAU8325_I2S_BP_SFT);
200 static constexpr uint16_t NAU8325_I2S_BP_INV = (0x1 << NAU8325_I2S_BP_SFT);
201 static constexpr uint16_t NAU8325_I2S_PCMB_SFT = 6;
202 static constexpr uint16_t NAU8325_I2S_PCMB_EN = (0x1 << NAU8325_I2S_PCMB_SFT);
203 static constexpr uint16_t NAU8325_I2S_DACPSHS0_SFT = 4;
204 static constexpr uint16_t NAU8325_I2S_DACPSHS0_MASK =
205 (0x3 << NAU8325_I2S_DACPSHS0_SFT);
206 static constexpr uint16_t NAU8325_I2S_DL_SFT = 2;
207 static constexpr uint16_t NAU8325_I2S_DL_MASK = (0x3 << NAU8325_I2S_DL_SFT);
208 static constexpr uint16_t NAU8325_I2S_DL_32 = (0x3 << NAU8325_I2S_DL_SFT);
209 static constexpr uint16_t NAU8325_I2S_DL_24 = (0x2 << NAU8325_I2S_DL_SFT);
210 static constexpr uint16_t NAU8325_I2S_DL_20 = (0x1 << NAU8325_I2S_DL_SFT);
211 static constexpr uint16_t NAU8325_I2S_DL_16 = (0x0 << NAU8325_I2S_DL_SFT);
212 static constexpr uint16_t NAU8325_I2S_DF_MASK = 0x3;
213 static constexpr uint16_t NAU8325_I2S_DF_RIGTH = 0x0;
214 static constexpr uint16_t NAU8325_I2S_DF_LEFT = 0x1;
215 static constexpr uint16_t NAU8325_I2S_DF_I2S = 0x2;
216 static constexpr uint16_t NAU8325_I2S_DF_PCM_AB = 0x3;
217 static constexpr uint16_t NAU8325_PCM_TS_SFT = 10;
218 static constexpr uint16_t NAU8325_PCM_TS_EN = (0x1 << NAU8325_PCM_TS_SFT);
219 static constexpr uint16_t NAU8325_PCM8BIT0_SFT = 8;
220 static constexpr uint16_t NAU8325_PCM8BIT0_MASK =
221 (0x3 << NAU8325_PCM8BIT0_SFT);
222 static constexpr uint16_t NAU8325_SHORT_FS_DET_SFT = 9;
223 static constexpr uint16_t NAU8325_SHORT_FS_DET_DIS =
224 (0x1 << NAU8325_SHORT_FS_DET_SFT);
225 static constexpr uint16_t NAU8325_TSLOT_L0_MASK = 0x1ff;
226 static constexpr uint16_t NAU8325_TSLOT_R0_MASK = 0x1ff;
227 static constexpr uint16_t NAU8325_DAC_HPF_SFT = 15;
228 static constexpr uint16_t NAU8325_DAC_HPF_EN = (0x1 << NAU8325_DAC_HPF_SFT);
229 static constexpr uint16_t NAU8325_DAC_HPF_APP_SFT = 4;
230 static constexpr uint16_t NAU8325_DAC_HPF_APP_MASK =
231 (0x1 << NAU8325_DAC_HPF_APP_SFT);
232 static constexpr uint32_t NAU8325_DAC_HPF_FCUT_SFT = 0;
233 static constexpr uint16_t NAU8325_DAC_HPF_FCUT_MASK =
234 (0xf << NAU8325_DAC_HPF_FCUT_SFT);
235 static constexpr uint16_t NAU8325_SOFT_MUTE_SFT = 9;
236 static constexpr uint16_t NAU8325_SOFT_MUTE = (0x1 << NAU8325_SOFT_MUTE_SFT);
237 static constexpr uint16_t NAU8325_DAC_ZC_SFT = 8;
238 static constexpr uint16_t NAU8325_DAC_ZC_EN = (0x1 << NAU8325_DAC_ZC_SFT);
239 static constexpr uint16_t NAU8325_UNMUTE_CTL_SFT = 6;
240 static constexpr uint16_t NAU8325_UNMUTE_CTL_MASK =
241 (0x3 << NAU8325_UNMUTE_CTL_SFT);
242 static constexpr uint16_t NAU8325_ANA_MUTE_SFT = 4;
243 static constexpr uint16_t NAU8325_ANA_MUTE_MASK =
244 (0x3 << NAU8325_ANA_MUTE_SFT);
245 static constexpr uint16_t NAU8325_AUTO_MUTE_SFT = 2;
246 static constexpr uint16_t NAU8325_AUTO_MUTE_DIS =
247 (0x1 << NAU8325_AUTO_MUTE_SFT);
248 static constexpr uint16_t NAU8325_DAC_VOLUME_L_SFT = 8;
249 static constexpr uint16_t NAU8325_DAC_VOLUME_L_EN =
250 (0xff << NAU8325_DAC_VOLUME_L_SFT);
251 static constexpr uint32_t NAU8325_DAC_VOLUME_R_SFT = 0;
252 static constexpr uint16_t NAU8325_DAC_VOLUME_R_EN =
253 (0xff << NAU8325_DAC_VOLUME_R_SFT);
254 static constexpr uint32_t NAU8325_DAC_VOL_MAX = 0xfe;
255 static constexpr uint16_t NAU8325_OSR100_MASK = (0x1 << 7);
256 static constexpr uint16_t NAU8325_MIPS500_MASK = (0x1 << 6);
257 static constexpr uint16_t NAU8325_SHUTDWNDRVR_R_MASK = (0x1 << 5);
258 static constexpr uint16_t NAU8325_SHUTDWNDRVR_L_MASK = (0x1 << 4);
259 static constexpr uint16_t NAU8325_MUTEB_MASK = (0x1 << 3);
260 static constexpr uint16_t NAU8325_PDOSCB_MASK = (0x1 << 2);
261 static constexpr uint16_t NAU8325_POWERDOWN1B_D_MASK = (0x1 << 1);
262 static constexpr uint16_t NAU8325_R_CHANNEL_Vol_SFT = 8;
263 static constexpr uint16_t NAU8325_R_CHANNEL_Vol_MASK =
264 (0x1f << NAU8325_R_CHANNEL_Vol_SFT);
265 static constexpr uint16_t NAU8325_L_CHANNEL_Vol_MASK = 0x1f;
266 static constexpr uint16_t NAU8325_PGAL_GAIN_MASK = (0x1f << 8);
267 static constexpr uint16_t NAU8325_CLIP_MASK = (0x1 << 7);
268 static constexpr uint16_t NAU8325_SCAN_MODE_MASK = (0x1 << 6);
269 static constexpr uint16_t NAU8325_SDB_MASK = (0x1 << 5);
270 static constexpr uint16_t NAU8325_TALARM_MASK = (0x1 << 4);
271 static constexpr uint16_t NAU8325_SHORTR_MASK = (0x1 << 3);
272 static constexpr uint16_t NAU8325_SHORTL_MASK = (0x1 << 2);
273 static constexpr uint16_t NAU8325_TMDET_MASK = 0x3;
274 static constexpr uint32_t NAU8325_DAC_OVERSAMPLE_SFT = 0;
275 static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_MASK =
276 (0x7 << NAU8325_DAC_OVERSAMPLE_SFT);
277 static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_256 =
278 (0x0 << NAU8325_DAC_OVERSAMPLE_SFT);
279 static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_128 =
280 (0x1 << NAU8325_DAC_OVERSAMPLE_SFT);
281 static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_64 =
282 (0x2 << NAU8325_DAC_OVERSAMPLE_SFT);
283 static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_32 =
284 (0x4 << NAU8325_DAC_OVERSAMPLE_SFT);
285 static constexpr uint16_t NAU8325_ALC_MAXGAIN_SFT = 8;
286 static constexpr uint32_t NAU8325_ALC_MAXGAIN_MAX = 7;
287 static constexpr uint16_t NAU8325_ALC_MAXGAIN_MASK =
288 (0x7 << NAU8325_ALC_MAXGAIN_SFT);
289 static constexpr uint32_t NAU8325_ALC_MINGAIN_MAX = 7;
290 static constexpr uint32_t NAU8325_ALC_MINGAIN_SFT = 4;
291 static constexpr uint32_t NAU8325_ALC_MINGAIN_MASK =
292 (0x7 << NAU8325_ALC_MINGAIN_SFT);
293 static constexpr uint16_t NAU8325_ALC_DCY_SFT = 12;
294 static constexpr uint32_t NAU8325_ALC_DCY_MAX = 0xf;
295 static constexpr uint16_t NAU8325_ALC_DCY_MASK = (0xf << NAU8325_ALC_DCY_SFT);
296 static constexpr uint16_t NAU8325_ALC_ATK_SFT = 8;
297 static constexpr uint32_t NAU8325_ALC_ATK_MAX = 0xf;
298 static constexpr uint16_t NAU8325_ALC_ATK_MASK = (0xf << NAU8325_ALC_ATK_SFT);
299 static constexpr uint16_t NAU8325_ALC_HLD_SFT = 4;
300 static constexpr uint32_t NAU8325_ALC_HLD_MAX = 0xf;
301 static constexpr uint16_t NAU8325_ALC_HLD_MASK = (0xf << NAU8325_ALC_HLD_SFT);
302 static constexpr uint32_t NAU8325_ALC_LVL_SFT = 0;
303 static constexpr uint32_t NAU8325_ALC_LVL_MAX = 0xf;
304 static constexpr uint16_t NAU8325_ALC_LVL_MASK = (0xf << NAU8325_ALC_LVL_SFT);
305 static constexpr uint16_t NAU8325_ALC_EN_SFT = 15;
306 static constexpr uint16_t NAU8325_ALC_EN = (0x1 << NAU8325_ALC_EN_SFT);
307 static constexpr uint16_t NAU8325_TEMP_COMP_ACT2_MASK = (0x1 << 5);
308 static constexpr uint16_t NAU8325_LPF_IN1_EN_SFT = 15;
309 static constexpr uint16_t NAU8325_LPF_IN1_EN =
310 (0x1 << NAU8325_LPF_IN1_EN_SFT);
311 static constexpr uint16_t NAU8325_LPF_IN1_TC_SFT = 12;
312 static constexpr uint16_t NAU8325_LPF_IN1_TC_MASK =
313 (0x7 << NAU8325_LPF_IN1_TC_SFT);
314 static constexpr uint16_t NAU8325_LPF_IN2_EN_SFT = 11;
315 static constexpr uint16_t NAU8325_LPF_IN2_EN =
316 (0x1 << NAU8325_LPF_IN2_EN_SFT);
317 static constexpr uint16_t NAU8325_LPF_IN2_TC_SFT = 8;
318 static constexpr uint16_t NAU8325_LPF_IN2_TC_MASK =
319 (0x7 << NAU8325_LPF_IN2_TC_SFT);
320 static constexpr uint16_t NAU8325_APWRUP_SFT = 15;
321 static constexpr uint16_t NAU8325_APWRUP_EN = (0x1 << NAU8325_APWRUP_SFT);
322 static constexpr uint32_t NAU8325_CLKPWRUP_SFT = 14;
323 static constexpr uint32_t NAU8325_CLKPWRUP_DIS =
324 (0x1 << NAU8325_CLKPWRUP_SFT);
325 static constexpr uint16_t NAU8325_PWRUP_DFT_SFT = 13;
326 static constexpr uint16_t NAU8325_PWRUP_DFT = (0x1 << NAU8325_PWRUP_DFT_SFT);
327 static constexpr uint16_t NAU8325_REG_SRATE_SFT = 10;
328 static constexpr uint16_t NAU8325_REG_SRATE_MASK =
329 (0x7 << NAU8325_REG_SRATE_SFT);
330 static constexpr uint16_t NAU8325_REG_ALT_SRATE_SFT = 9;
331 static constexpr uint16_t NAU8325_REG_ALT_SRATE_EN =
332 (0x1 << NAU8325_REG_ALT_SRATE_SFT);
333 static constexpr uint32_t NAU8325_REG_DIV_MAX = (0x1 << 8);
334 static constexpr uint16_t NAU8325_BIAS_VMID_SEL_SFT = 4;
335 static constexpr uint16_t NAU8325_BIAS_VMID_SEL_MASK =
336 (0x3 << NAU8325_BIAS_VMID_SEL_SFT);
337 static constexpr uint16_t NAU8325_VMDFSTENB_SFT = 14;
338 static constexpr uint16_t NAU8325_VMDFSTENB_MASK =
339 (0x3 << NAU8325_VMDFSTENB_SFT);
340 static constexpr uint16_t NAU8325_CLASSDEN_SFT = 12;
341 static constexpr uint16_t NAU8325_CLASSDEN_MASK =
342 (0x3 << NAU8325_CLASSDEN_SFT);
343 static constexpr uint32_t NAU8325_DACCLKEN_R_SFT = 10;
344 static constexpr uint32_t NAU8325_DACCLKEN_R_MASK =
345 (0x3 << NAU8325_DACCLKEN_R_SFT);
346 static constexpr uint16_t NAU8325_DACEN_R_SFT = 8;
347 static constexpr uint16_t NAU8325_DACEN_R_MASK = (0x3 << NAU8325_DACEN_R_SFT);
348 static constexpr uint32_t NAU8325_DACCLKEN_SFT = 6;
349 static constexpr uint32_t NAU8325_DACCLKEN_MASK =
350 (0x3 << NAU8325_DACCLKEN_SFT);
351 static constexpr uint16_t NAU8325_DACEN_SFT = 4;
352 static constexpr uint16_t NAU8325_DACEN_MASK = (0x3 << NAU8325_DACEN_SFT);
353 static constexpr uint16_t NAU8325_BIASEN_SFT = 2;
354 static constexpr uint16_t NAU8325_BIASEN_MASK = (0x3 << NAU8325_BIASEN_SFT);
355 static constexpr uint16_t NAU8325_VMIDEN_MASK = 0x3;
356 static constexpr uint16_t NAU8325_ANALOG_CTRL1_VMID_EN = (0x3 << 0);
357 static constexpr uint16_t NAU8325_ANALOG_CTRL1_CLASSD_EN = (0x3 << 12);
358 static constexpr uint16_t NAU8325_ANALOG_CTRL1_EN_MASK =
359 (NAU8325_ANALOG_CTRL1_VMID_EN | NAU8325_ANALOG_CTRL1_CLASSD_EN);
360 static constexpr uint16_t NAU8325_PWMMOD_SFT = 14;
361 static constexpr uint16_t NAU8325_PWMMOD_MASK = (0x3 << NAU8325_PWMMOD_SFT);
362 static constexpr uint16_t NAU8325_DACTEST_SFT = 8;
363 static constexpr uint16_t NAU8325_DACTEST_MASK = (0x7 << NAU8325_DACTEST_SFT);
364 static constexpr uint16_t NAU8325_DACREFCAP_SFT = 6;
365 static constexpr uint16_t NAU8325_DACREFCAP_MASK =
366 (0x3 << NAU8325_DACREFCAP_SFT);
367 static constexpr uint16_t NAU8325_POWER_DOWN_L_SFT = 8;
368 static constexpr uint16_t NAU8325_POWER_DOWN_L_MASK =
369 (0x3 << NAU8325_POWER_DOWN_L_SFT);
370 static constexpr uint16_t NAU8325_POWER_DOWN_R_SFT = 6;
371 static constexpr uint16_t NAU8325_POWER_DOWN_R_MASK =
372 (0x3 << NAU8325_POWER_DOWN_R_SFT);
373 static constexpr uint16_t NAU8325_CLASSD_FINE_SFT = 3;
374 static constexpr uint16_t NAU8325_CLASSD_FINE_MASK =
375 (0x7 << NAU8325_CLASSD_FINE_SFT);
376 static constexpr uint16_t NAU8325_CLASSD_COARSE_GAIN_MASK = 0x7;
377 static constexpr uint16_t NAU8325_CLASSD_OCPN_SFT = 8;
378 static constexpr uint16_t NAU8325_CLASSD_OCPN_MASK =
379 (0xf << NAU8325_CLASSD_OCPN_SFT);
380 static constexpr uint16_t NAU8325_CLASSD_OCPP_SFT = 4;
381 static constexpr uint16_t NAU8325_CLASSD_OCPP_MASK =
382 (0xf << NAU8325_CLASSD_OCPP_SFT);
383 static constexpr uint16_t NAU8325_CLASSD_SLEWN_MASK = 0xf;
384 static constexpr uint32_t NAU8325_MCLK_RANGE_SFT = 15;
385 static constexpr uint32_t NAU8325_MCLK_RANGE_EN =
386 (0x1 << NAU8325_MCLK_RANGE_SFT);
387 static constexpr uint32_t NAU8325_MCLK8XEN_SFT = 4;
388 static constexpr uint32_t NAU8325_MCLK8XEN_EN = (0x1 << NAU8325_MCLK8XEN_SFT);
389 static constexpr uint32_t NAU8325_MCLK4XEN_EN = (0x1 << 3);
390 static constexpr uint16_t NAU8325_VBATLOW_SFT = 14;
391 static constexpr uint16_t NAU8325_VBATLOW_MASK = (0x3 << NAU8325_VBATLOW_SFT);
392 static constexpr uint16_t NAU8325_VDDSPK_LIM_SFT = 8;
393 static constexpr uint16_t NAU8325_VDDSPK_LIM_EN =
394 (0x1 << NAU8325_VDDSPK_LIM_SFT);
395 static constexpr uint16_t NAU8325_VDDSPK_LIM_MASK = (0x7 << 9);
396 static constexpr uint16_t NAU8325_ANALOG_CTRL6_SPKL_EN = (0x1 << 2);
397 static constexpr uint16_t NAU8325_ANALOG_CTRL6_SPKR_EN = (0x1 << 1);
398 static constexpr uint16_t NAU8325_ANALOG_CTRL6_EN_MASK =
399 (NAU8325_ANALOG_CTRL6_SPKL_EN | NAU8325_ANALOG_CTRL6_SPKR_EN);
400 static constexpr uint16_t NAU8325_ANTI_CLIP_SFT = 15;
401 static constexpr uint16_t NAU8325_ANTI_CLIP_EN =
402 (0x1 << NAU8325_ANTI_CLIP_SFT);
403 static constexpr uint32_t NAU8325_CLK_DAC_DELAY_SFT = 4;
404 static constexpr uint32_t NAU8325_CLK_DAC_DELAY_EN =
405 (0xf << NAU8325_CLK_DAC_DELAY_SFT);
406 static constexpr uint16_t NAU8325_DACVREFSEL_SFT = 2;
407 static constexpr uint16_t NAU8325_DACVREFSEL_MASK =
408 (0x3 << NAU8325_DACVREFSEL_SFT);
409 static constexpr uint32_t CLK_DA_AD_MAX = 6144000;
410 static constexpr uint32_t MASTER_CLK_MIN = 2048000;
411 static constexpr uint32_t MASTER_CLK_MAX = 49152000;
412
413 static const RegDefault reg_defaults[];
414
415 inline static const SrcAttr mclk_n1_div[] = {{1, 0x0}, {2, 0x1}, {3, 0x2}};
416
417 inline static const SrcAttr mclk_n2_div[] = {
418 {0, 0x0}, {1, 0x1}, {2, 0x2}, {3, 0x3}, {4, 0x4}};
419
420 inline static const SrcAttr mclk_n3_mult[] = {
421 {0, 0x1}, {1, 0x2}, {2, 0x3}, {3, 0x4}};
422
423 inline static const OsrAttr osr_dac_sel[] = {
424 {64, 2}, // OSR 64, SRC 1/4
425 {256, 0}, // OSR 256, SRC 1
426 {128, 1}, // OSR 128, SRC 1/2
427 {0, 0},
428 {32, 3} // OSR 32, SRC 1/8
429 };
430
431 inline static const SRateAttr target_srate_table[] = {
432 {48000, 2, true, {12288000, 19200000, 24000000}},
433 {16000, 1, false, {4096000, 6400000, 8000000}},
434 {8000, 0, false, {2048000, 3200000, 4000000}},
435 {44100, 2, true, {11289600, 17640000, 22050000}},
436 {64000, 3, false, {16384000, 25600000, 32000000}},
437 {96000, 3, true, {24576000, 38400000, 48000000}},
438 {12000, 0, true, {3072000, 4800000, 6000000}},
439 {24000, 1, true, {6144000, 9600000, 12000000}},
440 {32000, 2, false, {8192000, 12800000, 16000000}}};
441
443 NAU8325(i2c_bus_handle_t wire) : i2c(wire), i2c_addr(NAU8325_I2C_ADDR) {}
444
446 bool begin(uint32_t fs, uint8_t bits_per_sample, uint16_t ratio) {
447 AD_LOGI("[NAU8325] beginDynamic() starting...");
448 AD_LOGI(" fs = %lu Hz", fs);
449 AD_LOGI(" ratio = %u Hz", ratio);
450 AD_LOGI(" bits = %u", bits_per_sample);
451
452 if (bits_per_sample != 16 && bits_per_sample != 24 && bits_per_sample != 32) {
453 AD_LOGI("[NAU8325] Unsupported bit width: %u\n", bits_per_sample);
454 return false;
455 }
456
457 set_ratio = ratio;
458 uint32_t mclk = fs * ratio;
459 resetChip();
460 delayMs(5);
461
462 if (!setSysClock(mclk)) return false;
463
464 if (!configureAudio(fs, mclk, bits_per_sample)) return false;
465
466 if (!setI2SFormat(I2S_STD, NORMAL_BCLK)) return false;
467
468 // ***********Analog + ALC + Vref Config ***********
469 initRegisters();
470
471 // Wait for analog to settle
472 delayMs(50);
473
474 // Enable Analog/Output Blocks (DAPM Equivalent)
475 enableDAPMBlocks();
476
477 // Set default volume AFTER analog path is ready
478 setVolume(0xFD, 0xFD);
479
480 softMute(false);
481
482 /*default powerOn*/
483 powerOn();
484
485 AD_LOGI("[NAU8325] beginDynamic() complete - sound should play");
486 return true;
487 }
488
490 bool begin(uint32_t fs, uint8_t bits) {
491 return begin(fs, bits, 256);
492 }
493
495 bool begin() {
496 return begin(44100, 16, 256);
497 }
498
500 uint16_t readDeviceId() {
501 uint16_t id;
502 if (readRegister(NAU8325_R02_DEVICE_ID, id)) {
503 return id;
504 } else {
505 return 0xFFFF;
506 }
507 }
508
510 void resetChip() {
511 writeRegister(0x0000, 0x0001);
512 delayMs(2);
513 writeRegister(0x0000, 0x0000);
514 delayMs(2);
515 }
516
518 void softMute(bool enable) {
519 writeRegisterBits(NAU8325_R12_MUTE_CTRL, NAU8325_SOFT_MUTE,
520 enable ? NAU8325_SOFT_MUTE : 0);
521 delayMs(30);
522 }
523
542
558
560 void setPowerUpDefault(bool enable) {
561 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, NAU8325_PWRUP_DFT,
562 enable ? NAU8325_PWRUP_DFT : 0);
563 }
564
569
571 void setVolume(uint8_t left, uint8_t right) {
572 uint16_t value = ((left & 0xFF) << 8) | (right & 0xFF);
573 writeRegister(NAU8325_R13_DAC_VOLUME, value);
574 }
575
576 private:
577 i2c_bus_handle_t i2c;
578 uint8_t i2c_addr = NAU8325_I2C_ADDR;
579 uint32_t fs = 0;
580 uint32_t mclk = 0;
581
582 uint16_t set_ratio = 0;
583 bool alc_enable = true;
584 bool clock_detection = true;
585 bool clock_det_data = true;
586 uint32_t dac_vref_microvolt = 2880000;
587 uint32_t vref_impedance_ohms = 125000;
588
590 void enableDAPMBlocks() {
591 writeRegisterBits(NAU8325_R04_ENA_CTRL, NAU8325_ENA_CTRL_DAC_EN_MASK,
592 NAU8325_ENA_CTRL_DAC_EN_MASK);
593
594 writeRegisterBits(NAU8325_R61_ANALOG_CONTROL_1, NAU8325_ANALOG_CTRL1_EN_MASK,
595 NAU8325_ANALOG_CTRL1_EN_MASK);
596
597 writeRegisterBits(NAU8325_R66_ANALOG_CONTROL_6, NAU8325_ANALOG_CTRL6_EN_MASK,
598 NAU8325_ANALOG_CTRL6_EN_MASK);
599 }
600
602 bool applySampleRateClocks(const SRateAttr* srate, int n1_sel,
603 int mclk_mult_sel, int n2_sel) {
604 if (!srate || n1_sel < 0 || n1_sel >= 3 || n2_sel < 0 || n2_sel >= 5) {
605 AD_LOGI("[NAU8325] Invalid N1/N2 divider index.");
606 return false;
607 }
608
609 AD_LOGI("--- Debugging clock dividers ---");
610 AD_LOGI("n1_sel=%d (val=%d)", n1_sel, mclk_n1_div[n1_sel].val);
611 AD_LOGI("n2_sel=%d (val=%d)", n2_sel, mclk_n2_div[n2_sel].val);
612 AD_LOGI("mult_sel=%d", mclk_mult_sel);
613
614 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL,
615 NAU8325_REG_SRATE_MASK | NAU8325_REG_DIV_MAX,
616 (srate->range << NAU8325_REG_SRATE_SFT) |
617 (srate->max ? NAU8325_REG_DIV_MAX : 0));
618 uint16_t clk_ctrl_val = 0;
619 clk_ctrl_val |= mclk_n2_div[n2_sel].val;
620 clk_ctrl_val |= mclk_n1_div[n1_sel].val << NAU8325_CLK_MUL_SRC_SFT;
621 if (mclk_mult_sel >= 0 && mclk_mult_sel <= 3)
622 clk_ctrl_val |= mclk_n3_mult[mclk_mult_sel].val << NAU8325_MCLK_SEL_SFT;
623
624 clk_ctrl_val |= 0x1000; // DAC_CLK = MCLK/2 (required!)
625
626 writeRegister(NAU8325_R03_CLK_CTRL, clk_ctrl_val);
627 writeRegister(NAU8325_R03_CLK_CTRL, clk_ctrl_val);
628
629 switch (mclk_mult_sel) {
630 case 2:
631 writeRegisterBits(NAU8325_R65_ANALOG_CONTROL_5, NAU8325_MCLK4XEN_EN,
632 NAU8325_MCLK4XEN_EN);
633 break;
634 case 3:
635 writeRegisterBits(NAU8325_R65_ANALOG_CONTROL_5,
636 NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN,
637 NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN);
638 break;
639 default:
640 writeRegisterBits(NAU8325_R65_ANALOG_CONTROL_5,
641 NAU8325_MCLK4XEN_EN | NAU8325_MCLK8XEN_EN, 0);
642 break;
643 }
644
645 return true;
646 }
647
649 int getMclkRatioAndN2Index(const SRateAttr* srate, int mclk_hz, int& n2_sel_out) {
650 int ratio = NAU8325_MCLK_FS_RATIO_NUM;
651
652 for (int i = 0; i < 5; i++) {
653 int div = mclk_n2_div[i].param;
654 int mclk_src = mclk_hz >> div;
655
656 if (srate->mclk_src[NAU8325_MCLK_FS_RATIO_256] == (uint32_t)mclk_src) {
657 ratio = NAU8325_MCLK_FS_RATIO_256;
658 n2_sel_out = i;
659 break;
660 }
661 if (srate->mclk_src[NAU8325_MCLK_FS_RATIO_400] == (uint32_t)mclk_src) {
662 ratio = NAU8325_MCLK_FS_RATIO_400;
663 n2_sel_out = i;
664 break;
665 }
666 if (srate->mclk_src[NAU8325_MCLK_FS_RATIO_500] == (uint32_t)mclk_src) {
667 ratio = NAU8325_MCLK_FS_RATIO_500;
668 n2_sel_out = i;
669 break;
670 }
671 }
672
673 return ratio;
674 }
675
677 const SRateAttr* getSRateAttr(int fs) {
678 for (size_t i = 0;
679 i < sizeof(target_srate_table) / sizeof(target_srate_table[0]); ++i) {
680 if (target_srate_table[i].fs == fs) {
681 return &target_srate_table[i];
682 }
683 }
684 return nullptr;
685 }
686
688 bool chooseClockSource(int fs, int mclk, const SRateAttr*& srate,
689 int& n1_sel, int& mult_sel, int& n2_sel) {
690 if (fs <= 0 || mclk <= 0) {
691 AD_LOGI("[NAU8325] Invalid fs or mclk.");
692 return false;
693 }
694
695 srate = getSRateAttr(fs);
696 if (!srate) {
697 AD_LOGI("[NAU8325] Unsupported fs: %d\n", fs);
698 return false;
699 }
700
701 int ratio = getMclkRatioAndN2Index(srate, mclk, n2_sel);
702 if (ratio != NAU8325_MCLK_FS_RATIO_NUM) {
703 n1_sel = 0;
704 mult_sel = -1;
705 AD_LOGI("[NAU8325] Direct match: fs=%d, mclk=%d → N2=%d (Ratio=%d)\n", fs,
706 mclk, n2_sel, ratio);
707 return true;
708 }
709
710 int mclk_max = 0;
711 int best_n1 = -1, best_mult = -1, best_n2 = -1;
712
713 for (int i = 0; i < 3; ++i) {
714 for (int j = 0; j < 4; ++j) {
715 int m = (mclk << mclk_n3_mult[j].param) / mclk_n1_div[i].param;
716 int r = getMclkRatioAndN2Index(srate, m, n2_sel);
717
718 if (r != NAU8325_MCLK_FS_RATIO_NUM && (m > mclk_max || best_n1 < i)) {
719 mclk_max = m;
720 best_n1 = i;
721 best_mult = j;
722 best_n2 = n2_sel;
723 }
724 }
725 }
726
727 if (mclk_max > 0) {
728 n1_sel = best_n1;
729 mult_sel = best_mult;
730 n2_sel = best_n2;
731
732 AD_LOGI(
733 "[NAU8325] Matched via N1/N3 combo: fs=%d, mclk=%d → N1=%d, "
734 "N3(mult)=%d, N2=%d\n",
735 fs, mclk, n1_sel, mult_sel, n2_sel);
736 AD_LOGI("[NAU8325] chooseClockSource(): fs=%d, mclk=%d\n", fs, mclk);
737
738 return true;
739 }
740
741 AD_LOGI("[NAU8325] Failed to match MCLK %d Hz with fs %d Hz\n", mclk, fs);
742 return false;
743 }
744
746 bool configureClocks(int fs, int mclk) {
747 const SRateAttr* srate = nullptr;
748 int n1_sel = 0, mult_sel = -1, n2_sel = 0;
749
750 if (!chooseClockSource(fs, mclk, srate, n1_sel, mult_sel, n2_sel)) {
751 AD_LOGI("[NAU8325] Failed to choose clock source for fs=%d, mclk=%d\n",
752 fs, mclk);
753 return false;
754 }
755
756 if (!applySampleRateClocks(srate, n1_sel, mult_sel, n2_sel)) {
757 AD_LOGI("[NAU8325] Failed to apply sample rate clocks.");
758 return false;
759 }
760 AD_LOGI("[NAU8325] configureClocks(): fs=%u, mclk=%u\n", fs, mclk);
761
762 return true;
763 }
764
766 const OsrAttr* getCurrentOSR() {
767 uint16_t value;
768 if (!readRegister(NAU8325_R29_DAC_CTRL1, value)) {
769 return nullptr;
770 }
771
772 uint8_t osr_index = value & NAU8325_DAC_OVERSAMPLE_MASK;
773
774 if (osr_index >= sizeof(osr_dac_sel) / sizeof(osr_dac_sel[0])) {
775 return nullptr;
776 }
777
778 return &osr_dac_sel[osr_index];
779 }
780
782 bool configureAudio(uint32_t fs, uint32_t mclk, uint8_t bits_per_sample) {
783 this->fs = fs;
784 this->mclk = mclk;
785
786 if (!configureClocks(fs, mclk)) {
787 return false;
788 }
789
790 writeRegisterBits(NAU8325_R29_DAC_CTRL1, NAU8325_DAC_OVERSAMPLE_MASK,
791 NAU8325_DAC_OVERSAMPLE_128);
792
793 const OsrAttr* osr = getCurrentOSR();
794 if (!osr || osr->osr == 0 || (fs * osr->osr > CLK_DA_AD_MAX)) {
795 AD_LOGI("[NAU8325] Invalid OSR or fs × OSR exceeds max.");
796 return false;
797 }
798
799 writeRegisterBits(NAU8325_R03_CLK_CTRL, NAU8325_CLK_DAC_SRC_MASK,
800 osr->clk_src << NAU8325_CLK_DAC_SRC_SFT);
801
802 uint16_t val_len = 0;
803 switch (bits_per_sample) {
804 case 16:
805 val_len = NAU8325_I2S_DL_16;
806 break;
807 case 20:
808 val_len = NAU8325_I2S_DL_20;
809 break;
810 case 24:
811 val_len = NAU8325_I2S_DL_24;
812 break;
813 case 32:
814 val_len = NAU8325_I2S_DL_32;
815 break;
816 default:
817 AD_LOGI("[NAU8325] Invalid bit width: %u\n", bits_per_sample);
818 return false;
819 }
820
821 writeRegisterBits(NAU8325_R0D_I2S_PCM_CTRL1, NAU8325_I2S_DL_MASK, val_len);
822
823 AD_LOGI("[NAU8325] configureAudio(): fs=%u, mclk=%u, bits=%u\n", fs, mclk,
824 bits_per_sample);
825
826 return true;
827 }
828
830 bool setI2SFormat(AudioI2SFormat format, ClockPolarity polarity) {
831 uint16_t ctrl1_val = 0;
832
833 if (polarity == INVERTED_BCLK) {
834 ctrl1_val |= NAU8325_I2S_BP_INV;
835 }
836
837 switch (format) {
838 case I2S_STD:
839 ctrl1_val |= NAU8325_I2S_DF_I2S;
840 break;
841 case LEFT_JUSTIFIED:
842 ctrl1_val |= NAU8325_I2S_DF_LEFT;
843 break;
844 case RIGHT_JUSTIFIED:
845 ctrl1_val |= NAU8325_I2S_DF_RIGTH;
846 break;
847 case DSP_A:
848 ctrl1_val |= NAU8325_I2S_DF_PCM_AB;
849 break;
850 case DSP_B:
851 ctrl1_val |= NAU8325_I2S_DF_PCM_AB | NAU8325_I2S_PCMB_EN;
852 break;
853 default:
854 return false;
855 }
856
857 return writeRegisterBits(
858 NAU8325_R0D_I2S_PCM_CTRL1,
859 NAU8325_I2S_DF_MASK | NAU8325_I2S_BP_MASK | NAU8325_I2S_PCMB_EN,
860 ctrl1_val);
861 }
862
864 bool setSysClock(uint32_t freq) {
865 if (freq < MASTER_CLK_MIN || freq > MASTER_CLK_MAX) {
866 AD_LOGI("[NAU8325] Invalid MCLK: %u Hz (allowed: %u - %u)\n", freq,
867 MASTER_CLK_MIN, MASTER_CLK_MAX);
868 return false;
869 }
870
871 this->mclk = freq;
872 AD_LOGI("[NAU8325] MCLK set to %u Hz\n", mclk);
873 return true;
874 }
875
877 void initRegisters() {
878 writeRegisterBits(NAU8325_R2C_ALC_CTRL1, NAU8325_ALC_MAXGAIN_MASK,
879 0x7 << NAU8325_ALC_MAXGAIN_SFT);
880 writeRegisterBits(
881 NAU8325_R2D_ALC_CTRL2,
882 NAU8325_ALC_DCY_MASK | NAU8325_ALC_ATK_MASK | NAU8325_ALC_HLD_MASK,
883 (0x5 << NAU8325_ALC_DCY_SFT) | (0x3 << NAU8325_ALC_ATK_SFT) |
884 (0x5 << NAU8325_ALC_HLD_SFT));
885
886 if (alc_enable) {
887 writeRegisterBits(NAU8325_R2E_ALC_CTRL3, NAU8325_ALC_EN, NAU8325_ALC_EN);
888 }
889
890 uint16_t clk_det_mask = NAU8325_CLKPWRUP_DIS | NAU8325_PWRUP_DFT;
891
892 if (clock_detection)
893 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, clk_det_mask, 0);
894 else
895 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, clk_det_mask,
896 NAU8325_CLKPWRUP_DIS);
897
898 if (clock_det_data)
899 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, NAU8325_APWRUP_EN,
900 NAU8325_APWRUP_EN);
901 else
902 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, NAU8325_APWRUP_EN, 0);
903
904 uint16_t vref_val = 0xFFFF;
905 if (dac_vref_microvolt == 1800000)
906 vref_val = 0 << NAU8325_DACVREFSEL_SFT;
907 else if (dac_vref_microvolt == 2700000)
908 vref_val = 1 << NAU8325_DACVREFSEL_SFT;
909 else if (dac_vref_microvolt == 2880000)
910 vref_val = 2 << NAU8325_DACVREFSEL_SFT;
911 else if (dac_vref_microvolt == 3060000)
912 vref_val = 3 << NAU8325_DACVREFSEL_SFT;
913
914 if (vref_val != 0xFFFF) {
915 writeRegisterBits(NAU8325_R73_RDAC, NAU8325_DACVREFSEL_MASK, vref_val);
916 } else {
917 AD_LOGI("[NAU8325] Invalid DAC Vref: %lu uV\n", dac_vref_microvolt);
918 }
919
920 writeRegisterBits(NAU8325_R63_ANALOG_CONTROL_3,
921 NAU8325_CLASSD_COARSE_GAIN_MASK, 0x4);
922 writeRegisterBits(NAU8325_R64_ANALOG_CONTROL_4, NAU8325_CLASSD_SLEWN_MASK,
923 0x7);
924
925 uint16_t vref_imp_val = 0xFFFF;
926 if (vref_impedance_ohms == 0)
927 vref_imp_val = 0 << NAU8325_BIAS_VMID_SEL_SFT;
928 else if (vref_impedance_ohms == 25000)
929 vref_imp_val = 1 << NAU8325_BIAS_VMID_SEL_SFT;
930 else if (vref_impedance_ohms == 125000)
931 vref_imp_val = 2 << NAU8325_BIAS_VMID_SEL_SFT;
932 else if (vref_impedance_ohms == 2500)
933 vref_imp_val = 3 << NAU8325_BIAS_VMID_SEL_SFT;
934
935 if (vref_imp_val != 0xFFFF) {
936 writeRegisterBits(NAU8325_R60_BIAS_ADJ, NAU8325_BIAS_VMID_SEL_MASK,
937 vref_imp_val);
938 } else {
939 AD_LOGI("[NAU8325] Invalid VMID impedance: %lu ohms\n",
940 vref_impedance_ohms);
941 }
942
943 writeRegisterBits(
944 NAU8325_R61_ANALOG_CONTROL_1,
945 NAU8325_DACEN_MASK | NAU8325_DACCLKEN_MASK | NAU8325_DACEN_R_MASK |
946 NAU8325_DACCLKEN_R_MASK | NAU8325_CLASSDEN_MASK |
947 NAU8325_VMDFSTENB_MASK | NAU8325_BIASEN_MASK | NAU8325_VMIDEN_MASK,
948 (0x1 << NAU8325_DACEN_SFT) | (0x1 << NAU8325_DACCLKEN_SFT) |
949 (0x1 << NAU8325_DACEN_R_SFT) | (0x1 << NAU8325_DACCLKEN_R_SFT) |
950 (0x1 << NAU8325_CLASSDEN_SFT) | (0x1 << NAU8325_VMDFSTENB_SFT) |
951 (0x1 << NAU8325_BIASEN_SFT) | (1 << NAU8325_VMIDEN_SFT));
952
953 if (alc_enable) {
954 writeRegisterBits(NAU8325_R2E_ALC_CTRL3, NAU8325_ALC_EN, NAU8325_ALC_EN);
955 }
956
957 uint16_t clk_det_mask1 = NAU8325_CLKPWRUP_DIS | NAU8325_PWRUP_DFT;
958
959 if (clock_detection)
960 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, clk_det_mask1, 0);
961 else
962 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, clk_det_mask1,
963 NAU8325_CLKPWRUP_DIS);
964
965 if (clock_det_data)
966 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, NAU8325_APWRUP_EN,
967 NAU8325_APWRUP_EN);
968 else
969 writeRegisterBits(NAU8325_R40_CLK_DET_CTRL, NAU8325_APWRUP_EN, 0);
970
971 writeRegisterBits(NAU8325_R29_DAC_CTRL1, NAU8325_DAC_OVERSAMPLE_MASK,
972 NAU8325_DAC_OVERSAMPLE_128);
973 }
974
976 bool writeRegisterBits(uint16_t reg, uint16_t mask, uint16_t value) {
977 uint16_t current;
978 if (!readRegister(reg, current)) return false;
979 uint16_t new_value = (current & ~mask) | (value & mask);
980 return writeRegister(reg, new_value);
981 }
982
984 bool writeRegister(uint16_t reg, uint16_t val) {
985 AD_LOGI("[WRITE] reg=0x%04X val=0x%04X\n", reg, val);
986
987 uint8_t regBuf[2] = {(uint8_t)((reg >> 8) & 0xFF), (uint8_t)(reg & 0xFF)};
988 uint8_t dataBuf[2] = {(uint8_t)((val >> 8) & 0xFF), (uint8_t)(val & 0xFF)};
989
990 return i2c_bus_write_bytes(this->i2c, i2c_addr, regBuf, sizeof(regBuf),
991 dataBuf, sizeof(dataBuf)) == RESULT_OK;
992 }
993
995 bool readRegister(uint16_t reg, uint16_t& value) {
996 uint8_t regBuf[2] = {(uint8_t)((reg >> 8) & 0xFF), (uint8_t)(reg & 0xFF)};
997 uint8_t dataBuf[2] = {0, 0};
998
999 if (i2c_bus_read_bytes(this->i2c, i2c_addr, regBuf, sizeof(regBuf), dataBuf,
1000 sizeof(dataBuf)) != RESULT_OK) {
1001 return false;
1002 }
1003
1004 value = ((uint16_t)dataBuf[0] << 8) | dataBuf[1];
1005 return true;
1006 }
1007};
1008
1009} // namespace audio_driver
API_I2C.h
RESULT_OK
#define RESULT_OK
Definition DriverCommon.h:74
AD_LOGI
#define AD_LOGI(...)
Definition Logger.h:13
audio_driver::NAU8325
Header-only driver for the Nuvoton NAU8325 Class-D amplifier with DAC.
Definition NAU8325.h:63
audio_driver::NAU8325::NAU8325_CLKPWRUP_SFT
static constexpr uint32_t NAU8325_CLKPWRUP_SFT
Definition NAU8325.h:322
audio_driver::NAU8325::NAU8325_PWR_INT_MASK
static constexpr uint16_t NAU8325_PWR_INT_MASK
Definition NAU8325.h:150
audio_driver::NAU8325::NAU8325_DEM_DITH_EN
static constexpr uint16_t NAU8325_DEM_DITH_EN
Definition NAU8325.h:156
audio_driver::NAU8325::NAU8325_POWER_DOWN_L_MASK
static constexpr uint16_t NAU8325_POWER_DOWN_L_MASK
Definition NAU8325.h:368
audio_driver::NAU8325::NAU8325_SHORTL_MASK
static constexpr uint16_t NAU8325_SHORTL_MASK
Definition NAU8325.h:272
audio_driver::NAU8325::NAU8325_L_CHANNEL_Vol_MASK
static constexpr uint16_t NAU8325_L_CHANNEL_Vol_MASK
Definition NAU8325.h:265
audio_driver::NAU8325::target_srate_table
static const SRateAttr target_srate_table[]
Definition NAU8325.h:431
audio_driver::NAU8325::NAU8325_SHUTDWNDRVR_R_MASK
static constexpr uint16_t NAU8325_SHUTDWNDRVR_R_MASK
Definition NAU8325.h:257
audio_driver::NAU8325::osr_dac_sel
static const OsrAttr osr_dac_sel[]
Definition NAU8325.h:423
audio_driver::NAU8325::NAU8325_IRQ_OUTPUT_EN
static constexpr uint16_t NAU8325_IRQ_OUTPUT_EN
Definition NAU8325.h:170
audio_driver::NAU8325::NAU8325_DACTEST_SFT
static constexpr uint16_t NAU8325_DACTEST_SFT
Definition NAU8325.h:362
audio_driver::NAU8325::NAU8325_R12_MUTE_CTRL
static constexpr uint16_t NAU8325_R12_MUTE_CTRL
Definition NAU8325.h:82
audio_driver::NAU8325::NAU8325_ALC_ATK_MASK
static constexpr uint16_t NAU8325_ALC_ATK_MASK
Definition NAU8325.h:298
audio_driver::NAU8325::NAU8325_VMIDEN_MASK
static constexpr uint16_t NAU8325_VMIDEN_MASK
Definition NAU8325.h:355
audio_driver::NAU8325::NAU8325_ARP_DWN_INT_SFT
static constexpr uint16_t NAU8325_ARP_DWN_INT_SFT
Definition NAU8325.h:130
audio_driver::NAU8325::NAU8325_ALC_ATK_SFT
static constexpr uint16_t NAU8325_ALC_ATK_SFT
Definition NAU8325.h:296
audio_driver::NAU8325::NAU8325_DAC_RIGHT_CH_EN_SFT
static constexpr uint16_t NAU8325_DAC_RIGHT_CH_EN_SFT
Definition NAU8325.h:124
audio_driver::NAU8325::NAU8325_POWER_DOWN_L_SFT
static constexpr uint16_t NAU8325_POWER_DOWN_L_SFT
Definition NAU8325.h:367
audio_driver::NAU8325::NAU8325_I2S_DF_PCM_AB
static constexpr uint16_t NAU8325_I2S_DF_PCM_AB
Definition NAU8325.h:216
audio_driver::NAU8325::NAU8325_R04_ENA_CTRL
static constexpr uint16_t NAU8325_R04_ENA_CTRL
Definition NAU8325.h:70
audio_driver::NAU8325::NAU8325_VMDFSTENB_MASK
static constexpr uint16_t NAU8325_VMDFSTENB_MASK
Definition NAU8325.h:338
audio_driver::NAU8325::NAU8325_R29_DAC_CTRL1
static constexpr uint16_t NAU8325_R29_DAC_CTRL1
Definition NAU8325.h:87
audio_driver::NAU8325::NAU8325_MCLK8XEN_SFT
static constexpr uint32_t NAU8325_MCLK8XEN_SFT
Definition NAU8325.h:387
audio_driver::NAU8325::NAU8325_PWRUP_DFT
static constexpr uint16_t NAU8325_PWRUP_DFT
Definition NAU8325.h:326
audio_driver::NAU8325::NAU8325_I2S_DL_16
static constexpr uint16_t NAU8325_I2S_DL_16
Definition NAU8325.h:211
audio_driver::NAU8325::NAU8325_CLK_DAC_SRC_MASK
static constexpr uint32_t NAU8325_CLK_DAC_SRC_MASK
Definition NAU8325.h:112
audio_driver::NAU8325::NAU8325_MCLK_SRC_MASK
static constexpr uint32_t NAU8325_MCLK_SRC_MASK
Definition NAU8325.h:120
audio_driver::NAU8325::NAU8325_CLASSD_FINE_SFT
static constexpr uint16_t NAU8325_CLASSD_FINE_SFT
Definition NAU8325.h:373
audio_driver::NAU8325::NAU8325_TDM_EN
static constexpr uint16_t NAU8325_TDM_EN
Definition NAU8325.h:180
audio_driver::NAU8325::NAU8325_OCP_OTP_SHTDWN_INT_MASK
static constexpr uint16_t NAU8325_OCP_OTP_SHTDWN_INT_MASK
Definition NAU8325.h:142
audio_driver::NAU8325::NAU8325_GAINZI3_MASK
static constexpr uint16_t NAU8325_GAINZI3_MASK
Definition NAU8325.h:158
audio_driver::NAU8325::NAU8325_CLK_MUL_SRC_SFT
static constexpr uint32_t NAU8325_CLK_MUL_SRC_SFT
Definition NAU8325.h:114
audio_driver::NAU8325::NAU8325_R_CHANNEL_Vol_SFT
static constexpr uint16_t NAU8325_R_CHANNEL_Vol_SFT
Definition NAU8325.h:262
audio_driver::NAU8325::NAU8325_I2S_DF_LEFT
static constexpr uint16_t NAU8325_I2S_DF_LEFT
Definition NAU8325.h:214
audio_driver::NAU8325::NAU8325_ALC_MINGAIN_MAX
static constexpr uint32_t NAU8325_ALC_MINGAIN_MAX
Definition NAU8325.h:289
audio_driver::NAU8325::NAU8325_R1F_DEBUG_READ2
static constexpr uint16_t NAU8325_R1F_DEBUG_READ2
Definition NAU8325.h:85
audio_driver::NAU8325::NAU8325_LPF_IN1_EN_SFT
static constexpr uint16_t NAU8325_LPF_IN1_EN_SFT
Definition NAU8325.h:308
audio_driver::NAU8325::NAU8325_R06_INT_CLR_STATUS
static constexpr uint16_t NAU8325_R06_INT_CLR_STATUS
Definition NAU8325.h:72
audio_driver::NAU8325::powerOff
void powerOff()
Powers off the analog and DAC blocks after soft-muting the output.
Definition NAU8325.h:544
audio_driver::NAU8325::NAU8325_REG_DATA_LEN
static constexpr uint32_t NAU8325_REG_DATA_LEN
Definition NAU8325.h:110
audio_driver::NAU8325::NAU8325_IRQ_PL_ACT_HIGH
static constexpr uint16_t NAU8325_IRQ_PL_ACT_HIGH
Definition NAU8325.h:161
audio_driver::NAU8325::NAU8325_I2C_ADDR
static constexpr uint16_t NAU8325_I2C_ADDR
Definition NAU8325.h:65
audio_driver::NAU8325::NAU8325_R01_SOFTWARE_RST
static constexpr uint16_t NAU8325_R01_SOFTWARE_RST
Definition NAU8325.h:67
audio_driver::NAU8325::NAU8325_IRQ_PIN_DEBUG_SFT
static constexpr uint16_t NAU8325_IRQ_PIN_DEBUG_SFT
Definition NAU8325.h:172
audio_driver::NAU8325::NAU8325_MUTEB_MASK
static constexpr uint16_t NAU8325_MUTEB_MASK
Definition NAU8325.h:259
audio_driver::NAU8325::NAU8325_REG_ADDR_LEN
static constexpr uint32_t NAU8325_REG_ADDR_LEN
Definition NAU8325.h:109
audio_driver::NAU8325::MASTER_CLK_MIN
static constexpr uint32_t MASTER_CLK_MIN
Definition NAU8325.h:410
audio_driver::NAU8325::NAU8325_CLASSD_OCPN_MASK
static constexpr uint16_t NAU8325_CLASSD_OCPN_MASK
Definition NAU8325.h:378
audio_driver::NAU8325::NAU8325_DAC_VOLUME_L_EN
static constexpr uint16_t NAU8325_DAC_VOLUME_L_EN
Definition NAU8325.h:249
audio_driver::NAU8325::NAU8325_CLKPWRUP_DIS
static constexpr uint32_t NAU8325_CLKPWRUP_DIS
Definition NAU8325.h:323
audio_driver::NAU8325::NAU8325_ANALOG_CTRL6_SPKL_EN
static constexpr uint16_t NAU8325_ANALOG_CTRL6_SPKL_EN
Definition NAU8325.h:396
audio_driver::NAU8325::NAU8325_POWER_DOWN_R_MASK
static constexpr uint16_t NAU8325_POWER_DOWN_R_MASK
Definition NAU8325.h:371
audio_driver::NAU8325::NAU8325_ALC_HLD_MASK
static constexpr uint16_t NAU8325_ALC_HLD_MASK
Definition NAU8325.h:301
audio_driver::NAU8325::NAU8325_DEM_DITH_SFT
static constexpr uint16_t NAU8325_DEM_DITH_SFT
Definition NAU8325.h:155
audio_driver::NAU8325::NAU8325_PCM_TS_SFT
static constexpr uint16_t NAU8325_PCM_TS_SFT
Definition NAU8325.h:217
audio_driver::NAU8325::NAU8325_ARP_DWN_INT_MASK
static constexpr uint16_t NAU8325_ARP_DWN_INT_MASK
Definition NAU8325.h:131
audio_driver::NAU8325::NAU8325_DACCLKEN_R_MASK
static constexpr uint32_t NAU8325_DACCLKEN_R_MASK
Definition NAU8325.h:344
audio_driver::NAU8325::NAU8325_CLIP_INT_DIS_SFT
static constexpr uint16_t NAU8325_CLIP_INT_DIS_SFT
Definition NAU8325.h:144
audio_driver::NAU8325::NAU8325_LVD_INT_DIS
static constexpr uint16_t NAU8325_LVD_INT_DIS
Definition NAU8325.h:148
audio_driver::NAU8325::NAU8325_IRQ_PE_SFT
static constexpr uint16_t NAU8325_IRQ_PE_SFT
Definition NAU8325.h:165
audio_driver::NAU8325::NAU8325_DAC_VOL_MAX
static constexpr uint32_t NAU8325_DAC_VOL_MAX
Definition NAU8325.h:254
audio_driver::NAU8325::begin
bool begin(uint32_t fs, uint8_t bits)
Initializes the codec with sample rate and bit depth; uses default MCLK/FS ratio of 256.
Definition NAU8325.h:490
audio_driver::NAU8325::NAU8325_REG_ALT_SRATE_EN
static constexpr uint16_t NAU8325_REG_ALT_SRATE_EN
Definition NAU8325.h:331
audio_driver::NAU8325::NAU8325_TEMP_COMP_ACT2_MASK
static constexpr uint16_t NAU8325_TEMP_COMP_ACT2_MASK
Definition NAU8325.h:307
audio_driver::NAU8325::NAU8325_PDM_LCH_EDGE__MASK
static constexpr uint16_t NAU8325_PDM_LCH_EDGE__MASK
Definition NAU8325.h:176
audio_driver::NAU8325::NAU8325_BIASEN_SFT
static constexpr uint16_t NAU8325_BIASEN_SFT
Definition NAU8325.h:353
audio_driver::NAU8325::NAU8325_IRQOUT_SEL_MASK
static constexpr uint16_t NAU8325_IRQOUT_SEL_MASK
Definition NAU8325.h:153
audio_driver::NAU8325::NAU8325_R2E_ALC_CTRL3
static constexpr uint16_t NAU8325_R2E_ALC_CTRL3
Definition NAU8325.h:91
audio_driver::NAU8325::resetChip
void resetChip()
Performs a hardware reset by toggling the reset register.
Definition NAU8325.h:510
audio_driver::NAU8325::NAU8325_DAC_HPF_APP_MASK
static constexpr uint16_t NAU8325_DAC_HPF_APP_MASK
Definition NAU8325.h:230
audio_driver::NAU8325::NAU8325_ANA_MUTE_SFT
static constexpr uint16_t NAU8325_ANA_MUTE_SFT
Definition NAU8325.h:242
audio_driver::NAU8325::NAU8325_R2C_ALC_CTRL1
static constexpr uint16_t NAU8325_R2C_ALC_CTRL1
Definition NAU8325.h:89
audio_driver::NAU8325::NAU8325_ALC_MINGAIN_MASK
static constexpr uint32_t NAU8325_ALC_MINGAIN_MASK
Definition NAU8325.h:291
audio_driver::NAU8325::NAU8325_REG_SRATE_MASK
static constexpr uint16_t NAU8325_REG_SRATE_MASK
Definition NAU8325.h:328
audio_driver::NAU8325::NAU8325_MCLK8XEN_EN
static constexpr uint32_t NAU8325_MCLK8XEN_EN
Definition NAU8325.h:388
audio_driver::NAU8325::NAU8325_ANTI_CLIP_SFT
static constexpr uint16_t NAU8325_ANTI_CLIP_SFT
Definition NAU8325.h:400
audio_driver::NAU8325::NAU8325_TDM_SFT
static constexpr uint16_t NAU8325_TDM_SFT
Definition NAU8325.h:179
audio_driver::NAU8325::NAU8325_DACCM_CTL_MASK
static constexpr uint16_t NAU8325_DACCM_CTL_MASK
Definition NAU8325.h:191
audio_driver::NAU8325::NAU8325_R50_MIXER_CTRL
static constexpr uint16_t NAU8325_R50_MIXER_CTRL
Definition NAU8325.h:96
audio_driver::NAU8325::NAU8325_GAINZI3_SFT
static constexpr uint16_t NAU8325_GAINZI3_SFT
Definition NAU8325.h:157
audio_driver::NAU8325::NAU8325_DACCLKEN_R_SFT
static constexpr uint32_t NAU8325_DACCLKEN_R_SFT
Definition NAU8325.h:343
audio_driver::NAU8325::NAU8325_I2S_DF_RIGTH
static constexpr uint16_t NAU8325_I2S_DF_RIGTH
Definition NAU8325.h:213
audio_driver::NAU8325::NAU8325_DAC_LEFT_SFT
static constexpr uint16_t NAU8325_DAC_LEFT_SFT
Definition NAU8325.h:184
audio_driver::NAU8325::NAU8325_R02_DEVICE_ID
static constexpr uint16_t NAU8325_R02_DEVICE_ID
Definition NAU8325.h:68
audio_driver::NAU8325::NAU8325_BIASEN_MASK
static constexpr uint16_t NAU8325_BIASEN_MASK
Definition NAU8325.h:354
audio_driver::NAU8325::NAU8325_CLK_DAC_SRC_SFT
static constexpr uint32_t NAU8325_CLK_DAC_SRC_SFT
Definition NAU8325.h:111
audio_driver::NAU8325::NAU8325_ANALOG_CTRL1_CLASSD_EN
static constexpr uint16_t NAU8325_ANALOG_CTRL1_CLASSD_EN
Definition NAU8325.h:357
audio_driver::NAU8325::NAU8325_R0F_L_TIME_SLOT
static constexpr uint16_t NAU8325_R0F_L_TIME_SLOT
Definition NAU8325.h:79
audio_driver::NAU8325::mclk_n1_div
static const SrcAttr mclk_n1_div[]
Definition NAU8325.h:415
audio_driver::NAU8325::NAU8325_DAC_HPF_FCUT_MASK
static constexpr uint16_t NAU8325_DAC_HPF_FCUT_MASK
Definition NAU8325.h:233
audio_driver::NAU8325::NAU8325_CLIP_INT_MASK
static constexpr uint16_t NAU8325_CLIP_INT_MASK
Definition NAU8325.h:134
audio_driver::NAU8325::NAU8325_PGAL_GAIN_MASK
static constexpr uint16_t NAU8325_PGAL_GAIN_MASK
Definition NAU8325.h:266
audio_driver::NAU8325::NAU8325_DACCLKEN_SFT
static constexpr uint32_t NAU8325_DACCLKEN_SFT
Definition NAU8325.h:348
audio_driver::NAU8325::NAU8325_DAC_RIGHT_SFT
static constexpr uint16_t NAU8325_DAC_RIGHT_SFT
Definition NAU8325.h:187
audio_driver::NAU8325::NAU8325_AUTO_MUTE_DIS
static constexpr uint16_t NAU8325_AUTO_MUTE_DIS
Definition NAU8325.h:246
audio_driver::NAU8325::reg_defaults
static const RegDefault reg_defaults[]
Definition NAU8325.h:413
audio_driver::NAU8325::NAU8325_DACTEST_MASK
static constexpr uint16_t NAU8325_DACTEST_MASK
Definition NAU8325.h:363
audio_driver::NAU8325::NAU8325_R64_ANALOG_CONTROL_4
static constexpr uint16_t NAU8325_R64_ANALOG_CONTROL_4
Definition NAU8325.h:102
audio_driver::NAU8325::NAU8325_TMDET_MASK
static constexpr uint16_t NAU8325_TMDET_MASK
Definition NAU8325.h:273
audio_driver::NAU8325::NAU8325_ANALOG_CTRL1_VMID_EN
static constexpr uint16_t NAU8325_ANALOG_CTRL1_VMID_EN
Definition NAU8325.h:356
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_256
static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_256
Definition NAU8325.h:277
audio_driver::NAU8325::NAU8325_R09_IRQOUT
static constexpr uint16_t NAU8325_R09_IRQOUT
Definition NAU8325.h:73
audio_driver::NAU8325::NAU8325_REG_MAX
static constexpr uint32_t NAU8325_REG_MAX
Definition NAU8325.h:107
audio_driver::NAU8325::NAU8325_R49_TEST_STATUS
static constexpr uint16_t NAU8325_R49_TEST_STATUS
Definition NAU8325.h:94
audio_driver::NAU8325::NAU8325_IRQ_DS_SFT
static constexpr uint16_t NAU8325_IRQ_DS_SFT
Definition NAU8325.h:167
audio_driver::NAU8325::NAU8325_CMB8_0_MASK
static constexpr uint16_t NAU8325_CMB8_0_MASK
Definition NAU8325.h:194
audio_driver::NAU8325::NAU8325_ALC_LVL_SFT
static constexpr uint32_t NAU8325_ALC_LVL_SFT
Definition NAU8325.h:302
audio_driver::NAU8325::NAU8325_PCM_OFFSET_CTRL_EN
static constexpr uint16_t NAU8325_PCM_OFFSET_CTRL_EN
Definition NAU8325.h:182
audio_driver::NAU8325::setVolume
void setVolume(uint8_t left, uint8_t right)
Sets the DAC digital volume for left and right channels (0x00–0xFE, 0xFF = mute)
Definition NAU8325.h:571
audio_driver::NAU8325::NAU8325_I2S_DACPSHS0_SFT
static constexpr uint16_t NAU8325_I2S_DACPSHS0_SFT
Definition NAU8325.h:203
audio_driver::NAU8325::NAU8325_VDDSPK_LIM_MASK
static constexpr uint16_t NAU8325_VDDSPK_LIM_MASK
Definition NAU8325.h:395
audio_driver::NAU8325::NAU8325
NAU8325(i2c_bus_handle_t wire)
Constructs the driver and binds it to the given I2C bus handle.
Definition NAU8325.h:443
audio_driver::NAU8325::NAU8325_MCLK_RANGE_EN
static constexpr uint32_t NAU8325_MCLK_RANGE_EN
Definition NAU8325.h:385
audio_driver::NAU8325::NAU8325_DACEN_SFT
static constexpr uint16_t NAU8325_DACEN_SFT
Definition NAU8325.h:351
audio_driver::NAU8325::NAU8325_LPF_IN1_TC_SFT
static constexpr uint16_t NAU8325_LPF_IN1_TC_SFT
Definition NAU8325.h:311
audio_driver::NAU8325::NAU8325_ALC_ATK_MAX
static constexpr uint32_t NAU8325_ALC_ATK_MAX
Definition NAU8325.h:297
audio_driver::NAU8325::NAU8325_I2S_BP_MASK
static constexpr uint16_t NAU8325_I2S_BP_MASK
Definition NAU8325.h:199
audio_driver::NAU8325::powerOn
void powerOn()
Powers on the analog and DAC blocks and unmutes the output.
Definition NAU8325.h:525
audio_driver::NAU8325::NAU8325_IRQ_DS_HIGH
static constexpr uint16_t NAU8325_IRQ_DS_HIGH
Definition NAU8325.h:168
audio_driver::NAU8325::NAU8325_BIAS_VMID_SEL_SFT
static constexpr uint16_t NAU8325_BIAS_VMID_SEL_SFT
Definition NAU8325.h:334
audio_driver::NAU8325::NAU8325_VDDSPK_LIM_SFT
static constexpr uint16_t NAU8325_VDDSPK_LIM_SFT
Definition NAU8325.h:392
audio_driver::NAU8325::CLK_DA_AD_MAX
static constexpr uint32_t CLK_DA_AD_MAX
Definition NAU8325.h:409
audio_driver::NAU8325::NAU8325_R0D_I2S_PCM_CTRL1
static constexpr uint16_t NAU8325_R0D_I2S_PCM_CTRL1
Definition NAU8325.h:77
audio_driver::NAU8325::begin
bool begin()
Initializes the codec with default settings (44100 Hz, 16-bit, ratio 256)
Definition NAU8325.h:495
audio_driver::NAU8325::NAU8325_I2S_DL_MASK
static constexpr uint16_t NAU8325_I2S_DL_MASK
Definition NAU8325.h:207
audio_driver::NAU8325::NAU8325_BIAS_VMID_SEL_MASK
static constexpr uint16_t NAU8325_BIAS_VMID_SEL_MASK
Definition NAU8325.h:335
audio_driver::NAU8325::NAU8325_ENA_CTRL_DAC_EN_MASK
static constexpr uint16_t NAU8325_ENA_CTRL_DAC_EN_MASK
Definition NAU8325.h:129
audio_driver::NAU8325::NAU8325_I2S_BP_INV
static constexpr uint16_t NAU8325_I2S_BP_INV
Definition NAU8325.h:200
audio_driver::NAU8325::NAU8325_CLASSD_FINE_MASK
static constexpr uint16_t NAU8325_CLASSD_FINE_MASK
Definition NAU8325.h:374
audio_driver::NAU8325::NAU8325_PWMMOD_MASK
static constexpr uint16_t NAU8325_PWMMOD_MASK
Definition NAU8325.h:361
audio_driver::NAU8325::NAU8325_I2S_BP_SFT
static constexpr uint16_t NAU8325_I2S_BP_SFT
Definition NAU8325.h:198
audio_driver::NAU8325::NAU8325_R2A_DAC_CTRL2
static constexpr uint16_t NAU8325_R2A_DAC_CTRL2
Definition NAU8325.h:88
audio_driver::NAU8325::NAU8325_CLK_DAC_DELAY_EN
static constexpr uint32_t NAU8325_CLK_DAC_DELAY_EN
Definition NAU8325.h:404
audio_driver::NAU8325::NAU8325_ALC_LVL_MAX
static constexpr uint32_t NAU8325_ALC_LVL_MAX
Definition NAU8325.h:303
audio_driver::NAU8325::NAU8325_ENA_CTRL_DACR_EN
static constexpr uint16_t NAU8325_ENA_CTRL_DACR_EN
Definition NAU8325.h:127
audio_driver::NAU8325::NAU8325_DACEN_R_SFT
static constexpr uint16_t NAU8325_DACEN_R_SFT
Definition NAU8325.h:346
audio_driver::NAU8325::NAU8325_IRQ_PL_SFT
static constexpr uint16_t NAU8325_IRQ_PL_SFT
Definition NAU8325.h:160
audio_driver::NAU8325::NAU8325_ALC_MINGAIN_SFT
static constexpr uint32_t NAU8325_ALC_MINGAIN_SFT
Definition NAU8325.h:290
audio_driver::NAU8325::NAU8325_OCP_OTP_SHTDWN_INT_SFT
static constexpr uint16_t NAU8325_OCP_OTP_SHTDWN_INT_SFT
Definition NAU8325.h:141
audio_driver::NAU8325::NAU8325_MCLK_RANGE_SFT
static constexpr uint32_t NAU8325_MCLK_RANGE_SFT
Definition NAU8325.h:384
audio_driver::NAU8325::NAU8325_R2D_ALC_CTRL2
static constexpr uint16_t NAU8325_R2D_ALC_CTRL2
Definition NAU8325.h:90
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_MASK
static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_MASK
Definition NAU8325.h:275
audio_driver::NAU8325::NAU8325_R4A_ANALOG_READ
static constexpr uint16_t NAU8325_R4A_ANALOG_READ
Definition NAU8325.h:95
audio_driver::NAU8325::NAU8325_R00_HARDWARE_RST
static constexpr uint16_t NAU8325_R00_HARDWARE_RST
Definition NAU8325.h:66
audio_driver::NAU8325::NAU8325_INT_STATUS_MASK
static constexpr uint16_t NAU8325_INT_STATUS_MASK
Definition NAU8325.h:151
audio_driver::NAU8325::NAU8325_SHORT_FS_DET_DIS
static constexpr uint16_t NAU8325_SHORT_FS_DET_DIS
Definition NAU8325.h:223
audio_driver::NAU8325::NAU8325_R22_DEBUG_READ3
static constexpr uint16_t NAU8325_R22_DEBUG_READ3
Definition NAU8325.h:86
audio_driver::NAU8325::NAU8325_R13_DAC_VOLUME
static constexpr uint16_t NAU8325_R13_DAC_VOLUME
Definition NAU8325.h:83
audio_driver::NAU8325::NAU8325_LVD_INT_MASK
static constexpr uint16_t NAU8325_LVD_INT_MASK
Definition NAU8325.h:137
audio_driver::NAU8325::NAU8325_ALC_DCY_MASK
static constexpr uint16_t NAU8325_ALC_DCY_MASK
Definition NAU8325.h:295
audio_driver::NAU8325::NAU8325_ANALOG_CTRL6_SPKR_EN
static constexpr uint16_t NAU8325_ANALOG_CTRL6_SPKR_EN
Definition NAU8325.h:397
audio_driver::NAU8325::setOversampling
void setOversampling(OversamplingMode mode)
Sets the DAC oversampling rate (OSR_32, OSR_64, OSR_128, or OSR_256)
Definition NAU8325.h:566
audio_driver::NAU8325::NAU8325_DACEN_R_MASK
static constexpr uint16_t NAU8325_DACEN_R_MASK
Definition NAU8325.h:347
audio_driver::NAU8325::NAU8325_PDM_MODE_EN
static constexpr uint16_t NAU8325_PDM_MODE_EN
Definition NAU8325.h:178
audio_driver::NAU8325::NAU8325_REG_ALT_SRATE_SFT
static constexpr uint16_t NAU8325_REG_ALT_SRATE_SFT
Definition NAU8325.h:330
audio_driver::NAU8325::NAU8325_ALC_HLD_MAX
static constexpr uint32_t NAU8325_ALC_HLD_MAX
Definition NAU8325.h:300
audio_driver::NAU8325::NAU8325_IRQOUT_SEL_SEF
static constexpr uint16_t NAU8325_IRQOUT_SEL_SEF
Definition NAU8325.h:152
audio_driver::NAU8325::NAU8325_UA_OFFSET_MASK
static constexpr uint16_t NAU8325_UA_OFFSET_MASK
Definition NAU8325.h:196
audio_driver::NAU8325::NAU8325_LPF_IN2_EN
static constexpr uint16_t NAU8325_LPF_IN2_EN
Definition NAU8325.h:315
audio_driver::NAU8325::NAU8325_R40_CLK_DET_CTRL
static constexpr uint32_t NAU8325_R40_CLK_DET_CTRL
Definition NAU8325.h:93
audio_driver::NAU8325::NAU8325_DAC_ZC_SFT
static constexpr uint16_t NAU8325_DAC_ZC_SFT
Definition NAU8325.h:237
audio_driver::NAU8325::NAU8325_I2S_DL_SFT
static constexpr uint16_t NAU8325_I2S_DL_SFT
Definition NAU8325.h:206
audio_driver::NAU8325::NAU8325_TSLOT_L0_MASK
static constexpr uint16_t NAU8325_TSLOT_L0_MASK
Definition NAU8325.h:225
audio_driver::NAU8325::NAU8325_CLIP_INT_DIS
static constexpr uint16_t NAU8325_CLIP_INT_DIS
Definition NAU8325.h:145
audio_driver::NAU8325::NAU8325_VBATLOW_SFT
static constexpr uint16_t NAU8325_VBATLOW_SFT
Definition NAU8325.h:390
audio_driver::NAU8325::NAU8325_PCM8BIT0_MASK
static constexpr uint16_t NAU8325_PCM8BIT0_MASK
Definition NAU8325.h:220
audio_driver::NAU8325::mclk_n3_mult
static const SrcAttr mclk_n3_mult[]
Definition NAU8325.h:420
audio_driver::NAU8325::mclk_n2_div
static const SrcAttr mclk_n2_div[]
Definition NAU8325.h:417
audio_driver::NAU8325::NAU8325_R05_INTERRUPT_CTRL
static constexpr uint16_t NAU8325_R05_INTERRUPT_CTRL
Definition NAU8325.h:71
audio_driver::NAU8325::NAU8325_SHORTR_MASK
static constexpr uint16_t NAU8325_SHORTR_MASK
Definition NAU8325.h:271
audio_driver::NAU8325::NAU8325_I2S_DF_I2S
static constexpr uint16_t NAU8325_I2S_DF_I2S
Definition NAU8325.h:215
audio_driver::NAU8325::NAU8325_MCLK_SEL_MASK
static constexpr uint32_t NAU8325_MCLK_SEL_MASK
Definition NAU8325.h:118
audio_driver::NAU8325::NAU8325_LPF_IN1_TC_MASK
static constexpr uint16_t NAU8325_LPF_IN1_TC_MASK
Definition NAU8325.h:312
audio_driver::NAU8325::NAU8325_R61_ANALOG_CONTROL_1
static constexpr uint16_t NAU8325_R61_ANALOG_CONTROL_1
Definition NAU8325.h:99
audio_driver::NAU8325::NAU8325_DACCLKEN_MASK
static constexpr uint32_t NAU8325_DACCLKEN_MASK
Definition NAU8325.h:349
audio_driver::NAU8325::NAU8325_R62_ANALOG_CONTROL_2
static constexpr uint16_t NAU8325_R62_ANALOG_CONTROL_2
Definition NAU8325.h:100
audio_driver::NAU8325::NAU8325_R0B_PDM_CTRL
static constexpr uint16_t NAU8325_R0B_PDM_CTRL
Definition NAU8325.h:75
audio_driver::NAU8325::NAU8325_IRQ_PS_SFT
static constexpr uint16_t NAU8325_IRQ_PS_SFT
Definition NAU8325.h:163
audio_driver::NAU8325::NAU8325_IRQ_PS_UP
static constexpr uint16_t NAU8325_IRQ_PS_UP
Definition NAU8325.h:164
audio_driver::NAU8325::NAU8325_R60_BIAS_ADJ
static constexpr uint16_t NAU8325_R60_BIAS_ADJ
Definition NAU8325.h:98
audio_driver::NAU8325::NAU8325_ALC_MAXGAIN_MAX
static constexpr uint32_t NAU8325_ALC_MAXGAIN_MAX
Definition NAU8325.h:286
audio_driver::NAU8325::NAU8325_DACREFCAP_SFT
static constexpr uint16_t NAU8325_DACREFCAP_SFT
Definition NAU8325.h:364
audio_driver::NAU8325::NAU8325_IRQ_PE_EN
static constexpr uint16_t NAU8325_IRQ_PE_EN
Definition NAU8325.h:166
audio_driver::NAU8325::NAU8325_DAC_HPF_SFT
static constexpr uint16_t NAU8325_DAC_HPF_SFT
Definition NAU8325.h:227
audio_driver::NAU8325::NAU8325_PDM_LCH_EDGE_SFT
static constexpr uint16_t NAU8325_PDM_LCH_EDGE_SFT
Definition NAU8325.h:175
audio_driver::NAU8325::NAU8325_TALARM_MASK
static constexpr uint16_t NAU8325_TALARM_MASK
Definition NAU8325.h:270
audio_driver::NAU8325::NAU8325_NAU8325_DAC_LEFT_MASK
static constexpr uint16_t NAU8325_NAU8325_DAC_LEFT_MASK
Definition NAU8325.h:185
audio_driver::NAU8325::NAU8325_REG_DIV_MAX
static constexpr uint32_t NAU8325_REG_DIV_MAX
Definition NAU8325.h:333
audio_driver::NAU8325::NAU8325_SDB_MASK
static constexpr uint16_t NAU8325_SDB_MASK
Definition NAU8325.h:269
audio_driver::NAU8325::NAU8325_R11_HPF_CTRL
static constexpr uint16_t NAU8325_R11_HPF_CTRL
Definition NAU8325.h:81
audio_driver::NAU8325::NAU8325_PWR_INT_DIS
static constexpr uint16_t NAU8325_PWR_INT_DIS
Definition NAU8325.h:139
audio_driver::NAU8325::NAU8325_LVD_INT_SFT
static constexpr uint16_t NAU8325_LVD_INT_SFT
Definition NAU8325.h:136
audio_driver::NAU8325::NAU8325_PCM_OFFSET_CTRL_SFT
static constexpr uint16_t NAU8325_PCM_OFFSET_CTRL_SFT
Definition NAU8325.h:181
audio_driver::NAU8325::NAU8325_IRQ_PIN_DEBUG_EN
static constexpr uint16_t NAU8325_IRQ_PIN_DEBUG_EN
Definition NAU8325.h:173
audio_driver::NAU8325::NAU8325_SCAN_MODE_MASK
static constexpr uint16_t NAU8325_SCAN_MODE_MASK
Definition NAU8325.h:268
audio_driver::NAU8325::NAU8325_DACVREFSEL_SFT
static constexpr uint16_t NAU8325_DACVREFSEL_SFT
Definition NAU8325.h:406
audio_driver::NAU8325::NAU8325_ALC_MAXGAIN_MASK
static constexpr uint16_t NAU8325_ALC_MAXGAIN_MASK
Definition NAU8325.h:287
audio_driver::NAU8325::NAU8325_DAC_HPF_EN
static constexpr uint16_t NAU8325_DAC_HPF_EN
Definition NAU8325.h:228
audio_driver::NAU8325::NAU8325_CLASSD_OCPP_SFT
static constexpr uint16_t NAU8325_CLASSD_OCPP_SFT
Definition NAU8325.h:380
audio_driver::NAU8325::NAU8325_LPF_IN2_TC_SFT
static constexpr uint16_t NAU8325_LPF_IN2_TC_SFT
Definition NAU8325.h:317
audio_driver::NAU8325::NAU8325_DAC_HPF_FCUT_SFT
static constexpr uint32_t NAU8325_DAC_HPF_FCUT_SFT
Definition NAU8325.h:232
audio_driver::NAU8325::NAU8325_SHORT_FS_DET_SFT
static constexpr uint16_t NAU8325_SHORT_FS_DET_SFT
Definition NAU8325.h:222
audio_driver::NAU8325::NAU8325_DACVREFSEL_MASK
static constexpr uint16_t NAU8325_DACVREFSEL_MASK
Definition NAU8325.h:407
audio_driver::NAU8325::NAU8325_DAC_LEFT_CH_EN
static constexpr uint16_t NAU8325_DAC_LEFT_CH_EN
Definition NAU8325.h:122
audio_driver::NAU8325::NAU8325_MCLK_SEL_SFT
static constexpr uint32_t NAU8325_MCLK_SEL_SFT
Definition NAU8325.h:117
audio_driver::NAU8325::NAU8325_ALC_HLD_SFT
static constexpr uint16_t NAU8325_ALC_HLD_SFT
Definition NAU8325.h:299
audio_driver::NAU8325::NAU8325_ANA_MUTE_MASK
static constexpr uint16_t NAU8325_ANA_MUTE_MASK
Definition NAU8325.h:243
audio_driver::NAU8325::NAU8325_PDOSCB_MASK
static constexpr uint16_t NAU8325_PDOSCB_MASK
Definition NAU8325.h:260
audio_driver::NAU8325::NAU8325_APWRUP_SFT
static constexpr uint16_t NAU8325_APWRUP_SFT
Definition NAU8325.h:320
audio_driver::NAU8325::NAU8325_ALC_MAXGAIN_SFT
static constexpr uint16_t NAU8325_ALC_MAXGAIN_SFT
Definition NAU8325.h:285
audio_driver::NAU8325::NAU8325_CLIP_INT_SFT
static constexpr uint16_t NAU8325_CLIP_INT_SFT
Definition NAU8325.h:133
audio_driver::NAU8325::NAU8325_MIPS500_MASK
static constexpr uint16_t NAU8325_MIPS500_MASK
Definition NAU8325.h:256
audio_driver::NAU8325::NAU8325_DAC_RIGHT_CH_EN
static constexpr uint16_t NAU8325_DAC_RIGHT_CH_EN
Definition NAU8325.h:125
audio_driver::NAU8325::NAU8325_I2S_DACPSHS0_MASK
static constexpr uint16_t NAU8325_I2S_DACPSHS0_MASK
Definition NAU8325.h:204
audio_driver::NAU8325::NAU8325_VMDFSTENB_SFT
static constexpr uint16_t NAU8325_VMDFSTENB_SFT
Definition NAU8325.h:337
audio_driver::NAU8325::NAU8325_R0C_TDM_CTRL
static constexpr uint16_t NAU8325_R0C_TDM_CTRL
Definition NAU8325.h:76
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_128
static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_128
Definition NAU8325.h:279
audio_driver::NAU8325::NAU8325_UNMUTE_CTL_MASK
static constexpr uint16_t NAU8325_UNMUTE_CTL_MASK
Definition NAU8325.h:240
audio_driver::NAU8325::NAU8325_I2S_DL_24
static constexpr uint16_t NAU8325_I2S_DL_24
Definition NAU8325.h:209
audio_driver::NAU8325::NAU8325_OSR100_MASK
static constexpr uint16_t NAU8325_OSR100_MASK
Definition NAU8325.h:255
audio_driver::NAU8325::NAU8325_LVD_INT_DIS_SFT
static constexpr uint16_t NAU8325_LVD_INT_DIS_SFT
Definition NAU8325.h:147
audio_driver::NAU8325::NAU8325_DAC_ZC_EN
static constexpr uint16_t NAU8325_DAC_ZC_EN
Definition NAU8325.h:238
audio_driver::NAU8325::softMute
void softMute(bool enable)
Enables or disables soft mute on the DAC output.
Definition NAU8325.h:518
audio_driver::NAU8325::NAU8325_R10_R_TIME_SLOT
static constexpr uint16_t NAU8325_R10_R_TIME_SLOT
Definition NAU8325.h:80
audio_driver::NAU8325::NAU8325_R69_CLIP_CTRL
static constexpr uint16_t NAU8325_R69_CLIP_CTRL
Definition NAU8325.h:105
audio_driver::NAU8325::NAU8325_IRQ_OUTPUT_SFT
static constexpr uint16_t NAU8325_IRQ_OUTPUT_SFT
Definition NAU8325.h:169
audio_driver::NAU8325::NAU8325_CLASSDEN_SFT
static constexpr uint16_t NAU8325_CLASSDEN_SFT
Definition NAU8325.h:340
audio_driver::NAU8325::NAU8325_LPF_IN1_EN
static constexpr uint16_t NAU8325_LPF_IN1_EN
Definition NAU8325.h:309
audio_driver::NAU8325::NAU8325_DAC_VOLUME_R_EN
static constexpr uint16_t NAU8325_DAC_VOLUME_R_EN
Definition NAU8325.h:252
audio_driver::NAU8325::NAU8325_UNMUTE_CTL_SFT
static constexpr uint16_t NAU8325_UNMUTE_CTL_SFT
Definition NAU8325.h:239
audio_driver::NAU8325::NAU8325_PWR_INT_DIS_SFT
static constexpr uint16_t NAU8325_PWR_INT_DIS_SFT
Definition NAU8325.h:138
audio_driver::NAU8325::NAU8325_DAC_LEFT_CH_EN_SFT
static constexpr uint16_t NAU8325_DAC_LEFT_CH_EN_SFT
Definition NAU8325.h:121
audio_driver::NAU8325::NAU8325_I2S_DF_MASK
static constexpr uint16_t NAU8325_I2S_DF_MASK
Definition NAU8325.h:212
audio_driver::NAU8325::NAU8325_R_CHANNEL_Vol_MASK
static constexpr uint16_t NAU8325_R_CHANNEL_Vol_MASK
Definition NAU8325.h:263
audio_driver::NAU8325::NAU8325_ANTI_CLIP_EN
static constexpr uint16_t NAU8325_ANTI_CLIP_EN
Definition NAU8325.h:401
audio_driver::NAU8325::NAU8325_R1D_DEBUG_READ1
static constexpr uint16_t NAU8325_R1D_DEBUG_READ1
Definition NAU8325.h:84
audio_driver::NAU8325::NAU8325_LPF_IN2_TC_MASK
static constexpr uint16_t NAU8325_LPF_IN2_TC_MASK
Definition NAU8325.h:318
audio_driver::NAU8325::NAU8325_PWMMOD_SFT
static constexpr uint16_t NAU8325_PWMMOD_SFT
Definition NAU8325.h:360
audio_driver::NAU8325::NAU8325_ENA_CTRL_DACL_EN
static constexpr uint16_t NAU8325_ENA_CTRL_DACL_EN
Definition NAU8325.h:128
audio_driver::NAU8325::NAU8325_I2S_PCMB_SFT
static constexpr uint16_t NAU8325_I2S_PCMB_SFT
Definition NAU8325.h:201
audio_driver::NAU8325::NAU8325_I2S_PCMB_EN
static constexpr uint16_t NAU8325_I2S_PCMB_EN
Definition NAU8325.h:202
audio_driver::NAU8325::NAU8325_CLK_MUL_SRC_MASK
static constexpr uint32_t NAU8325_CLK_MUL_SRC_MASK
Definition NAU8325.h:115
audio_driver::NAU8325::NAU8325_PCM_TS_EN
static constexpr uint16_t NAU8325_PCM_TS_EN
Definition NAU8325.h:218
audio_driver::NAU8325::NAU8325_DACREFCAP_MASK
static constexpr uint16_t NAU8325_DACREFCAP_MASK
Definition NAU8325.h:365
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_SFT
static constexpr uint32_t NAU8325_DAC_OVERSAMPLE_SFT
Definition NAU8325.h:274
audio_driver::NAU8325::NAU8325_PCM8BIT0_SFT
static constexpr uint16_t NAU8325_PCM8BIT0_SFT
Definition NAU8325.h:219
audio_driver::NAU8325::NAU8325_MCLK4XEN_EN
static constexpr uint32_t NAU8325_MCLK4XEN_EN
Definition NAU8325.h:389
audio_driver::NAU8325::NAU8325_I2S_DL_20
static constexpr uint16_t NAU8325_I2S_DL_20
Definition NAU8325.h:210
audio_driver::NAU8325::NAU8325_SOFT_MUTE_SFT
static constexpr uint16_t NAU8325_SOFT_MUTE_SFT
Definition NAU8325.h:235
audio_driver::NAU8325::begin
bool begin(uint32_t fs, uint8_t bits_per_sample, uint16_t ratio)
Initializes the codec with explicit sample rate, bit depth, and MCLK/FS ratio.
Definition NAU8325.h:446
audio_driver::NAU8325::NAU8325_DACCM_CTL_SFT
static constexpr uint16_t NAU8325_DACCM_CTL_SFT
Definition NAU8325.h:190
audio_driver::NAU8325::NAU8325_CMB8_0_SFT
static constexpr uint16_t NAU8325_CMB8_0_SFT
Definition NAU8325.h:193
audio_driver::NAU8325::NAU8325_R03_CLK_CTRL
static constexpr uint32_t NAU8325_R03_CLK_CTRL
Definition NAU8325.h:69
audio_driver::NAU8325::NAU8325_GAINZI2_MASK
static constexpr uint16_t NAU8325_GAINZI2_MASK
Definition NAU8325.h:159
audio_driver::NAU8325::NAU8325_POWER_DOWN_R_SFT
static constexpr uint16_t NAU8325_POWER_DOWN_R_SFT
Definition NAU8325.h:370
audio_driver::NAU8325::NAU8325_I2S_DL_32
static constexpr uint16_t NAU8325_I2S_DL_32
Definition NAU8325.h:208
audio_driver::NAU8325::NAU8325_ALC_EN
static constexpr uint16_t NAU8325_ALC_EN
Definition NAU8325.h:306
audio_driver::NAU8325::NAU8325_APWRUP_EN
static constexpr uint16_t NAU8325_APWRUP_EN
Definition NAU8325.h:321
audio_driver::NAU8325::NAU8325_PWRUP_DFT_SFT
static constexpr uint16_t NAU8325_PWRUP_DFT_SFT
Definition NAU8325.h:325
audio_driver::NAU8325::MASTER_CLK_MAX
static constexpr uint32_t MASTER_CLK_MAX
Definition NAU8325.h:411
audio_driver::NAU8325::NAU8325_POWERDOWN1B_D_MASK
static constexpr uint16_t NAU8325_POWERDOWN1B_D_MASK
Definition NAU8325.h:261
audio_driver::NAU8325::readDeviceId
uint16_t readDeviceId()
Reads and returns the device ID register; returns 0xFFFF on failure.
Definition NAU8325.h:500
audio_driver::NAU8325::NAU8325_ALC_DCY_SFT
static constexpr uint16_t NAU8325_ALC_DCY_SFT
Definition NAU8325.h:293
audio_driver::NAU8325::NAU8325_AUTO_MUTE_SFT
static constexpr uint16_t NAU8325_AUTO_MUTE_SFT
Definition NAU8325.h:245
audio_driver::NAU8325::NAU8325_CLASSD_SLEWN_MASK
static constexpr uint16_t NAU8325_CLASSD_SLEWN_MASK
Definition NAU8325.h:383
audio_driver::NAU8325::NAU8325_R73_RDAC
static constexpr uint16_t NAU8325_R73_RDAC
Definition NAU8325.h:106
audio_driver::NAU8325::NAU8325_ALC_EN_SFT
static constexpr uint16_t NAU8325_ALC_EN_SFT
Definition NAU8325.h:305
audio_driver::NAU8325::NAU8325_SOFT_MUTE
static constexpr uint16_t NAU8325_SOFT_MUTE
Definition NAU8325.h:236
audio_driver::NAU8325::NAU8325_R65_ANALOG_CONTROL_5
static constexpr uint16_t NAU8325_R65_ANALOG_CONTROL_5
Definition NAU8325.h:103
audio_driver::NAU8325::NAU8325_VMIDEN_SFT
static constexpr uint16_t NAU8325_VMIDEN_SFT
Definition NAU8325.h:108
audio_driver::NAU8325::NAU8325_CLASSD_OCPN_SFT
static constexpr uint16_t NAU8325_CLASSD_OCPN_SFT
Definition NAU8325.h:377
audio_driver::NAU8325::NAU8325_CLASSD_OCPP_MASK
static constexpr uint16_t NAU8325_CLASSD_OCPP_MASK
Definition NAU8325.h:381
audio_driver::NAU8325::NAU8325_DAC_VOLUME_R_SFT
static constexpr uint32_t NAU8325_DAC_VOLUME_R_SFT
Definition NAU8325.h:251
audio_driver::NAU8325::NAU8325_R0E_I2S_PCM_CTRL2
static constexpr uint16_t NAU8325_R0E_I2S_PCM_CTRL2
Definition NAU8325.h:78
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_32
static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_32
Definition NAU8325.h:283
audio_driver::NAU8325::NAU8325_R55_MISC_CTRL
static constexpr uint16_t NAU8325_R55_MISC_CTRL
Definition NAU8325.h:97
audio_driver::NAU8325::NAU8325_UA_OFFSET_SFT
static constexpr uint16_t NAU8325_UA_OFFSET_SFT
Definition NAU8325.h:195
audio_driver::NAU8325::NAU8325_ALC_DCY_MAX
static constexpr uint32_t NAU8325_ALC_DCY_MAX
Definition NAU8325.h:294
audio_driver::NAU8325::NAU8325_ANALOG_CTRL6_EN_MASK
static constexpr uint16_t NAU8325_ANALOG_CTRL6_EN_MASK
Definition NAU8325.h:398
audio_driver::NAU8325::NAU8325_CLASSD_COARSE_GAIN_MASK
static constexpr uint16_t NAU8325_CLASSD_COARSE_GAIN_MASK
Definition NAU8325.h:376
audio_driver::NAU8325::setPowerUpDefault
void setPowerUpDefault(bool enable)
Enables or disables the power-up default flag in the clock detection register.
Definition NAU8325.h:560
audio_driver::NAU8325::NAU8325_DACEN_MASK
static constexpr uint16_t NAU8325_DACEN_MASK
Definition NAU8325.h:352
audio_driver::NAU8325::NAU8325_SHUTDWNDRVR_L_MASK
static constexpr uint16_t NAU8325_SHUTDWNDRVR_L_MASK
Definition NAU8325.h:258
audio_driver::NAU8325::NAU8325_R2F_ALC_CTRL4
static constexpr uint16_t NAU8325_R2F_ALC_CTRL4
Definition NAU8325.h:92
audio_driver::NAU8325::NAU8325_REG_SRATE_SFT
static constexpr uint16_t NAU8325_REG_SRATE_SFT
Definition NAU8325.h:327
audio_driver::NAU8325::NAU8325_R0A_IO_CTRL
static constexpr uint16_t NAU8325_R0A_IO_CTRL
Definition NAU8325.h:74
audio_driver::NAU8325::NAU8325_CLK_DAC_DELAY_SFT
static constexpr uint32_t NAU8325_CLK_DAC_DELAY_SFT
Definition NAU8325.h:403
audio_driver::NAU8325::NAU8325_VBATLOW_MASK
static constexpr uint16_t NAU8325_VBATLOW_MASK
Definition NAU8325.h:391
audio_driver::NAU8325::NAU8325_CLASSDEN_MASK
static constexpr uint16_t NAU8325_CLASSDEN_MASK
Definition NAU8325.h:341
audio_driver::NAU8325::NAU8325_ALC_LVL_MASK
static constexpr uint16_t NAU8325_ALC_LVL_MASK
Definition NAU8325.h:304
audio_driver::NAU8325::NAU8325_DAC_RIGHT_MASK
static constexpr uint16_t NAU8325_DAC_RIGHT_MASK
Definition NAU8325.h:188
audio_driver::NAU8325::NAU8325_DAC_HPF_APP_SFT
static constexpr uint16_t NAU8325_DAC_HPF_APP_SFT
Definition NAU8325.h:229
audio_driver::NAU8325::NAU8325_TSLOT_R0_MASK
static constexpr uint16_t NAU8325_TSLOT_R0_MASK
Definition NAU8325.h:226
audio_driver::NAU8325::NAU8325_VDDSPK_LIM_EN
static constexpr uint16_t NAU8325_VDDSPK_LIM_EN
Definition NAU8325.h:393
audio_driver::NAU8325::NAU8325_DAC_OVERSAMPLE_64
static constexpr uint16_t NAU8325_DAC_OVERSAMPLE_64
Definition NAU8325.h:281
audio_driver::NAU8325::NAU8325_LPF_IN2_EN_SFT
static constexpr uint16_t NAU8325_LPF_IN2_EN_SFT
Definition NAU8325.h:314
audio_driver::NAU8325::NAU8325_DAC_VOLUME_L_SFT
static constexpr uint16_t NAU8325_DAC_VOLUME_L_SFT
Definition NAU8325.h:248
audio_driver::NAU8325::NAU8325_CLIP_MASK
static constexpr uint16_t NAU8325_CLIP_MASK
Definition NAU8325.h:267
audio_driver::NAU8325::NAU8325_R63_ANALOG_CONTROL_3
static constexpr uint16_t NAU8325_R63_ANALOG_CONTROL_3
Definition NAU8325.h:101
audio_driver::NAU8325::NAU8325_ANALOG_CTRL1_EN_MASK
static constexpr uint16_t NAU8325_ANALOG_CTRL1_EN_MASK
Definition NAU8325.h:358
audio_driver::NAU8325::NAU8325_R66_ANALOG_CONTROL_6
static constexpr uint16_t NAU8325_R66_ANALOG_CONTROL_6
Definition NAU8325.h:104
audio_driver
Namespace for audio driver components.
Definition AudioBoard.h:5
audio_driver::AudioI2SFormat
AudioI2SFormat
Definition NAU8325.h:32
audio_driver::DSP_A
@ DSP_A
Definition NAU8325.h:32
audio_driver::DSP_B
@ DSP_B
Definition NAU8325.h:32
audio_driver::RIGHT_JUSTIFIED
@ RIGHT_JUSTIFIED
Definition NAU8325.h:32
audio_driver::LEFT_JUSTIFIED
@ LEFT_JUSTIFIED
Definition NAU8325.h:32
audio_driver::I2S_STD
@ I2S_STD
Definition NAU8325.h:32
audio_driver::delayMs
void delayMs(unsigned long ms)
Definition API_Delay.h:19
audio_driver::ClockPolarity
ClockPolarity
Definition NAU8325.h:33
audio_driver::NORMAL_BCLK
@ NORMAL_BCLK
Definition NAU8325.h:33
audio_driver::INVERTED_BCLK
@ INVERTED_BCLK
Definition NAU8325.h:33
audio_driver::OversamplingMode
OversamplingMode
Definition NAU8325.h:34
audio_driver::OSR_128
@ OSR_128
Definition NAU8325.h:34
audio_driver::OSR_256
@ OSR_256
Definition NAU8325.h:34
audio_driver::OSR_64
@ OSR_64
Definition NAU8325.h:34
audio_driver::OSR_32
@ OSR_32
Definition NAU8325.h:34
audio_driver::ClockRatio
ClockRatio
Definition NAU8325.h:36
audio_driver::NAU8325_MCLK_FS_RATIO_NUM
@ NAU8325_MCLK_FS_RATIO_NUM
Definition NAU8325.h:40
audio_driver::NAU8325_MCLK_FS_RATIO_500
@ NAU8325_MCLK_FS_RATIO_500
Definition NAU8325.h:39
audio_driver::NAU8325_MCLK_FS_RATIO_256
@ NAU8325_MCLK_FS_RATIO_256
Definition NAU8325.h:37
audio_driver::NAU8325_MCLK_FS_RATIO_400
@ NAU8325_MCLK_FS_RATIO_400
Definition NAU8325.h:38
audio_driver::i2c_bus_handle_t
void * i2c_bus_handle_t
Definition DriverCommon.h:155
audio_driver::OsrAttr
Definition NAU8325.h:15
audio_driver::OsrAttr::clk_src
uint8_t clk_src
Definition NAU8325.h:17
audio_driver::OsrAttr::osr
int osr
Definition NAU8325.h:16
audio_driver::RegDefault
Definition NAU8325.h:27
audio_driver::RegDefault::reg
uint16_t reg
Definition NAU8325.h:28
audio_driver::RegDefault::val
uint16_t val
Definition NAU8325.h:29
audio_driver::SRateAttr
Definition NAU8325.h:20
audio_driver::SRateAttr::mclk_src
uint32_t mclk_src[3]
Definition NAU8325.h:24
audio_driver::SRateAttr::max
bool max
Definition NAU8325.h:23
audio_driver::SRateAttr::fs
int fs
Definition NAU8325.h:21
audio_driver::SRateAttr::range
uint8_t range
Definition NAU8325.h:22
audio_driver::SrcAttr
Definition NAU8325.h:10
audio_driver::SrcAttr::param
int param
Definition NAU8325.h:11
audio_driver::SrcAttr::val
uint8_t val
Definition NAU8325.h:12
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