#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>

Macros
#define	WM8960_I2C_ADDRESS (0x1A)

#define	WM8960_LOG(msg)

#define	MTB_RSLT_WM8960_BAD_ARG false

WM8960_REG_LEFT_IN_VOL (0x00) and WM8960_REG_RIGHT_IN_VOL (0x01)
Bit definitions for the WM8960_REG_LEFT_IN_VOL and WM8960_REG_RIGHT_IN_VOL register
#define	WM8960_LEFT_RIGHT_IN_VOL_IPVU 0x100u

#define	WM8960_LEFT_RIGHT_IN_VOL_INMUTE 0x080u

#define	WM8960_LEFT_RIGHT_IN_VOL_IZC_ZC 0x040u

#define	WM8960_LEFT_RIGHT_IN_VOL_INVOL_0dB 0x017u

#define	WM8960_LEFT_RIGHT_IN_VOL_INVOL_30dB 0x03Fu

WM8960_REG_LOUT1_VOL (0x02) and WM8960_REG_ROUT1_VOL (0x03)
Bit definitions for the WM8960_REG_LOUT1_VOL and WM8960_REG_ROUT1_VOL register.
#define	WM8960_LOUT1_ROUT1_VOL_OUT1VU 0x100u

#define	WM8960_LOUT1_ROUT1_VOL_O1ZC_ZC 0x080u

#define	WM8960_LOUT1_ROUT1_VOL_OUT1VOL_0dB 0x079u

#define	WM8960_LOUT1_ROUT1_VOL_OUT1VOL_6dB 0x07Fu

WM8960_REG_CLK1 (0x04)
Bit definitions for the WM8960_REG_CLK1 register.
#define	WM8960_CLK1_ADCDIV_BY_1 0x000u

#define	WM8960_CLK1_ADCDIV_BY_1_5 0x040u

#define	WM8960_CLK1_ADCDIV_BY_2 0x080u

#define	WM8960_CLK1_ADCDIV_BY_3 0x0C0u

#define	WM8960_CLK1_ADCDIV_BY_4 0x100u

#define	WM8960_CLK1_ADCDIV_BY_5_5 0x140u

#define	WM8960_CLK1_ADCDIV_BY_6 0x180u

#define	WM8960_CLK1_DACDIV_BY_1 0x000u

#define	WM8960_CLK1_DACDIV_BY_1_5 0x008u

#define	WM8960_CLK1_DACDIV_BY_2 0x010u

#define	WM8960_CLK1_DACDIV_BY_3 0x018u

#define	WM8960_CLK1_DACDIV_BY_4 0x020u

#define	WM8960_CLK1_DACDIV_BY_5_5 0x028u

#define	WM8960_CLK1_DACDIV_BY_6 0x030u

#define	WM8960_CLK1_SYSCLKDIV_BY_1 0x000u

#define	WM8960_CLK1_SYSCLKDIV_BY_2 0x004u

#define	WM8960_CLK1_CLKSEL_MCLK 0x000u

#define	WM8960_CLK1_CLKSEL_PLL 0x001u

WM8960_REG_CTR1 (0x05)
Bit definitions for the WM8960_REG_CTR1 register.
#define	WM8960_CTR1_DACDIV2_6B_EN 0x080u

#define	WM8960_CTR1_ADCPOL_LR_INV 0x060u

#define	WM8960_CTR1_ADCPOL_L_INV 0x040u

#define	WM8960_CTR1_ADCPOL_R_INV 0x020u

#define	WM8960_CTR1_DACMU_NO 0x000u

#define	WM8960_CTR1_DACMU_MUTE 0x008u

#define	WM8960_CTR1_DEEMPH_48_KHZ 0x006u

#define	WM8960_CTR1_DEEMPH_44_1_KHZ 0x004u

#define	WM8960_CTR1_DEEMPH_32_KHZ 0x002u

#define	WM8960_CTR1_ADCHPD_DIS 0x001u

WM8960_REG_CTR2 (0x06)
Bit definitions for the WM8960_REG_CTR2 register.
#define	WM8960_CTR2_DACPOL_LR_INV 0x060u

#define	WM8960_CTR2_DACPOL_L_INV 0x040u

#define	WM8960_CTR2_DACPOL_R_INV 0x020u

#define	WM8960_CTR2_DACSMM_GRAD 0x008u

#define	WM8960_CTR2_DACMR_SLOW_RMP 0x004u

#define	WM8960_CTR2_DACSLOPE_SS 0x002u

WM8960_REG_AUDIO_INTF0 (0x07)
Bit definitions for the WM8960_REG_AUDIO_INTF0 register.
#define	WM8960_AUDIO_INTF0_ALRSWAP 0x100u

#define	WM8960_AUDIO_INTF0_BCLKINV 0x080u

#define	WM8960_AUDIO_INTF0_MS_MASTER 0x040u

#define	WM8960_AUDIO_INTF0_MS_SLAVE 0x000u

#define	WM8960_AUDIO_INTF0_DLRSWAP 0x020u

#define	WM8960_AUDIO_INTF0_LRP_INV 0x010u

#define	WM8960_AUDIO_INTF0_WL_16BITS 0x000u

#define	WM8960_AUDIO_INTF0_WL_20BITS 0x004u

#define	WM8960_AUDIO_INTF0_WL_24BITS 0x008u

#define	WM8960_AUDIO_INTF0_WL_32BITS 0x00Cu

#define	WM8960_AUDIO_INTF0_FORMAT_R_JUSTIF 0x000u

#define	WM8960_AUDIO_INTF0_FORMAT_L_JUSTIF 0x001u

#define	WM8960_AUDIO_INTF0_FORMAT_I2S_MODE 0x002u

#define	WM8960_AUDIO_INTF0_FORMAT_DSP_MODE 0x003u

WM8960_REG_CLK2 (0x08)
Bit definitions for the WM8960_REG_CLK2 register.
#define	WM8960_CLK2_DCLKDIV_BY_2 0x040u

#define	WM8960_CLK2_DCLKDIV_BY_3 0x080u

#define	WM8960_CLK2_DCLKDIV_BY_4 0x0C0u

#define	WM8960_CLK2_DCLKDIV_BY_6 0x100u

#define	WM8960_CLK2_DCLKDIV_BY_8 0x140u

#define	WM8960_CLK2_DCLKDIV_BY_12 0x180u

#define	WM8960_CLK2_DCLKDIV_BY_16 0x1C0u

#define	WM8960_CLK2_BCLKDIV_BY_1_5 0x001u

#define	WM8960_CLK2_BCLKDIV_BY_2 0x002u

#define	WM8960_CLK2_BCLKDIV_BY_3 0x003u

#define	WM8960_CLK2_BCLKDIV_BY_4 0x004u

#define	WM8960_CLK2_BCLKDIV_BY_5_5 0x005u

#define	WM8960_CLK2_BCLKDIV_BY_6 0x006u

#define	WM8960_CLK2_BCLKDIV_BY_8 0x007u

#define	WM8960_CLK2_BCLKDIV_BY_11 0x008u

#define	WM8960_CLK2_BCLKDIV_BY_12 0x009u

#define	WM8960_CLK2_BCLKDIV_BY_16 0x00Au

#define	WM8960_CLK2_BCLKDIV_BY_22 0x00Bu

#define	WM8960_CLK2_BCLKDIV_BY_24 0x00Cu

#define	WM8960_CLK2_BCLKDIV_BY_32 0x00Du

WM8960_REG_AUDIO_INTF1 (0x09)
Bit definitions for the WM8960_REG_AUDIO_INTF1 register.
#define	WM8960_AUDIO_INTF1_ALRCGPIO_GPIO 0x040u

#define	WM8960_AUDIO_INTF1_WL8_8BIT 0x020u

#define	WM8960_AUDIO_INTF1_DACCOMP_ALAW 0x010u

#define	WM8960_AUDIO_INTF1_DACCOMP_ULAW 0x018u

#define	WM8960_AUDIO_INTF1_ADCCOMP_ULAW 0x004u

#define	WM8960_AUDIO_INTF1_ADCCOMP_ALAW 0x006u

#define	WM8960_AUDIO_INTF1_LOOPBACK_EN 0x001u

WM8960_REG_LEFT_DAC_VOL (0x0A) and WM8960_REG_RIGHT_DAC_VOL (0x0B)
Bit definitions for the WM8960_REG_LEFT_DAC_VOL and WM8960_REG_RIGHT_DAC_VOL register.
#define	WM8960_LEFT_RIGHT_DAC_VOL_DACVU_UP 0x100u

#define	WM8960_LEFT_RIGHT_DAC_VOL_0dB 0x0FFu

#define	WM8960_LEFT_RIGHT_DAC_VOL_127dB 0x001u

WM8960_REG_3D_CTR (0x10)
Bit definitions for the WM8960_REG_3D_CTR register.
#define	WM8960_3D_CTR_3DUC_LOW 0x040u

#define	WM8960_3D_CTR_3DUC_HIGH 0x000u

#define	WM8960_3D_CTR_3DLC_LOW 0x000u

#define	WM8960_3D_CTR_3DLC_HIGH 0x020u

#define	WM8960_3D_CTR_3DDEPTH_100 0x01Eu

#define	WM8960_3D_CTR_3DEN 0x001u

WM8960_REG_LEFT_ADC_VOL (0x15) and WM8960_REG_RIGHT_ADC_VOL (0x16)
Bit definitions for the WM8960_REG_LEFT_ADC_VOL and WM8960_REG_LEFT_ADC_VOL register
#define	WM8960_LEFT_RIGHT_ADC_VOL_ADCVU_UP 0x100u

#define	WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_0dB 0x0C3u

#define	WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_30dB 0x0FFu

WM8960_REG_PWR_MGMT1 (0x19)
Bit definitions for the WM8960_REG_PWR_MGMT1 register
#define	WM8960_PWR_MGMT1_VMIDSEL_50K 0x080u

#define	WM8960_PWR_MGMT1_VMIDSEL_250K 0x100u

#define	WM8960_PWR_MGMT1_VMIDSEL_5K 0x180u

#define	WM8960_PWR_MGMT1_VREF_UP 0x040u

#define	WM8960_PWR_MGMT1_AINL_UP 0x020u

#define	WM8960_PWR_MGMT1_AINR_UP 0x010u

#define	WM8960_PWR_MGMT1_ADCL_UP 0x008u

#define	WM8960_PWR_MGMT1_ADCR_UP 0x004u

#define	WM8960_PWR_MGMT1_MICB_UP 0x002u

#define	WM8960_PWR_MGMT1_DIGENB_DI 0x001u

WM8960_REG_PWR_MGMT2 (0x1A)
Bit definitions for the WM8960_REG_PWR_MGMT2 register
#define	WM8960_PWR_MGMT2_DACL_UP 0x100u

#define	WM8960_PWR_MGMT2_DACR_UP 0x080u

#define	WM8960_PWR_MGMT2_LOUT1_UP 0x040u

#define	WM8960_PWR_MGMT2_ROUT1_UP 0x020u

#define	WM8960_PWR_MGMT2_SPKL_UP 0x010u

#define	WM8960_PWR_MGMT2_SPKR_UP 0x008u

#define	WM8960_PWR_MGMT2_OUT3_UP 0x002u

#define	WM8960_PWR_MGMT2_PLL_EN_UP 0x001u

WM8960_REG_ADCL_SIG_PTH (0x20) and WM8960_REG_ADCR_SIG_PTH (0x21)
Bit definitions for the WM8960_REG_ADCL_SIG_PTH and WM8960_REG_ADCR_SIG_PTH register
#define	WM8960_ADCL_ADCR_SIG_PTH_MN1_CON 0x100u

#define	WM8960_ADCL_ADCR_SIG_PTH_MP3_CON 0x080u

#define	WM8960_ADCL_ADCR_SIG_PTH_MP2_CON 0x040u

#define	WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_0dB 0x000u

#define	WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_13dB 0x010u

#define	WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_20dB 0x020u

#define	WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_29dB 0x030u

#define	WM8960_ADCL_ADCR_SIG_PTH_MIC2B_CON 0x008u

WM8960_REG_LEFT_OUT_MIX (0x22)
Bit definitions for the WM8960_REG_LEFT_OUT_MIX register
#define	WM8960_LEFT_OUT_MIX_LD2LO_EN 0x100u

#define	WM8960_LEFT_OUT_MIX_LI2LO_EN 0x080u

WM8960_REG_RIGHT_OUT_MIX (0x25)
Bit definitions for the WM8960_REG_RIGHT_OUT_MIX register
#define	WM8960_RIGHT_OUT_MIX_RD2RO_EN 0x100u

#define	WM8960_RIGHT_OUT_MIX_RI2RO_EN 0x080u

WM8960_REG_MONO_OUT_MIX1 (0x26)
and WM8960_REG_MONO_OUT_MIX2 (0x27) Bit definitions for the WM8960_REG_MONO_OUT_MIX1 and WM8960_REG_MONO_OUT_MIX2 register.
#define	WM8960_MONO_OUT_MIX1_MIX2_2MO_DI 0x000u

#define	WM8960_MONO_OUT_MIX1_MIX2_2MO_EN 0x080u

WM8960_REG_LOUT2_VOL (0x28)
and WM8960_REG_ROUT2_VOL (0x29) Bit definitions for the WM8960_REG_LOUT2_VOL and WM8960_REG_ROUT2_VOL register
#define	WM8960_LOUT2_ROUT2_VOL_SPKVU 0x100u

#define	WM8960_LOUT2_ROUT2_VOL_SPKRZC 0x080u

#define	WM8960_LOUT2_ROUT2_VOL_SPKRVOL_0dB 0x079u

#define	WM8960_LOUT2_ROUT2_VOL_SPKRVOL_6dB 0x07Fu

WM8960_REG_PWR_MGMT3 (0x2F)
Bit definitions for the WM8960_REG_PWR_MGMT3 register
#define	WM8960_PWR_MGMT3_LMIC_UP 0x020u

#define	WM8960_PWR_MGMT3_RMIC_UP 0x010u

#define	WM8960_PWR_MGMT3_LOMIX_UP 0x008u

#define	WM8960_PWR_MGMT3_ROMIX_UP 0x004u

WM8960_REG_PLL_N (0x34)
Bit definitions for the WM8960_REG_PWR_MGMT3 register
#define	WM8960_PLL_N_PLLPRESCALE_DI 0x000u

#define	WM8960_PLL_N_PLLPRESCALE_EN 0x010u

#define	WM8960_PLL_N_SDM_INT 0x000u

#define	WM8960_PLL_N_SDM_FRAC 0x020u

#define	WM8960_PLL_N_OPCLKDIV_BY_1 0x000u

#define	WM8960_PLL_N_OPCLKDIV_BY_2 0x040u

#define	WM8960_PLL_N_OPCLKDIV_BY_3 0x080u

#define	WM8960_PLL_N_OPCLKDIV_BY_4 0x0C0u

#define	WM8960_PLL_N_OPCLKDIV_BY_5_5 0x100u

#define	WM8960_PLL_N_OPCLKDIV_BY_6 0x140u

Enumerations
enum	mtb_wm8960_reg_t { WM8960_REG_LEFT_IN_VOL , WM8960_REG_RIGHT_IN_VOL , WM8960_REG_LOUT1_VOL , WM8960_REG_ROUT1_VOL , WM8960_REG_CLK1 , WM8960_REG_CTR1 , WM8960_REG_CTR2 , WM8960_REG_AUDIO_INTF0 , WM8960_REG_CLK2 , WM8960_REG_AUDIO_INTF1 , WM8960_REG_LEFT_DAC_VOL , WM8960_REG_RIGHT_DAC_VOL , WM8960_REG_RSVD0 , WM8960_REG_RSVD1 , WM8960_REG_RSVD2 , WM8960_REG_RESET , WM8960_REG_3D_CTR , WM8960_REG_ALC1 , WM8960_REG_ALC2 , WM8960_REG_ALC3 , WM8960_REG_NOISE_GATE , WM8960_REG_LEFT_ADC_VOL , WM8960_REG_RIGHT_ADC_VOL , WM8960_REG_ADD_CTL1 , WM8960_REG_ADD_CTL2 , WM8960_REG_PWR_MGMT1 , WM8960_REG_PWR_MGMT2 , WM8960_REG_ADD_CTL3 , WM8960_REG_ANTI_POP1 , WM8960_REG_ANTI_POP2 , WM8960_REG_RSVD3 , WM8960_REG_RSVD4 , WM8960_REG_ADCL_SIG_PTH , WM8960_REG_ADCR_SIG_PTH , WM8960_REG_LEFT_OUT_MIX , WM8960_REG_RSVD5 , WM8960_REG_RSVD6 , WM8960_REG_RIGHT_OUT_MIX , WM8960_REG_MONO_OUT_MIX1 , WM8960_REG_MONO_OUT_MIX2 , WM8960_REG_LOUT2_VOL , WM8960_REG_ROUT2_VOL , WM8960_REG_MONO_OUT_VOL , WM8960_REG_IN_BOOST_MIX1 , WM8960_REG_IN_BOOST_MIX2 , WM8960_REG_BYPASS1 , WM8960_REG_BYPASS2 , WM8960_REG_PWR_MGMT3 , WM8960_REG_ADD_CTL4 , WM8960_REG_CLASS_D_CTL1 , WM8960_REG_RSVD7 , WM8960_REG_CLASS_D_CTL3 , WM8960_REG_PLL_N , WM8960_REG_PLL_K1 , WM8960_REG_PLL_K2 , WM8960_REG_PLL_K3 }

enum	mtb_wm8960_features_t { WM8960_FEATURE_NONE = 0x00 , WM8960_FEATURE_MICROPHONE = 0x01 , WM8960_FEATURE_HEADPHONE = 0x02 , WM8960_FEATURE_SPEAKER = 0x04 }

enum	mtb_wm8960_adc_dac_sample_rate_t { WM8960_ADC_DAC_SAMPLE_RATE_48_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_44_1_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_32_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_24_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_22_05_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_16_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_12_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_11_025_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_8_018_KHZ , WM8960_ADC_DAC_SAMPLE_RATE_8_KHZ }

enum	mtb_wm8960_word_length_t { WM8960_WL_16BITS = WM8960_AUDIO_INTF0_WL_16BITS , WM8960_WL_20BITS = WM8960_AUDIO_INTF0_WL_20BITS , WM8960_WL_24BITS = WM8960_AUDIO_INTF0_WL_24BITS , WM8960_WL_32BITS = WM8960_AUDIO_INTF0_WL_32BITS }

enum	mtb_wm8960_mode_t { WM8960_MODE_MASTER = WM8960_AUDIO_INTF0_MS_MASTER , WM8960_MODE_SLAVE = WM8960_AUDIO_INTF0_MS_SLAVE }

Functions
void	mtb_wm8960_set_write_retry_count (uint32_t count)
	Defines the number of times we retry to update a register value via I2C. This might help if you have an instable I2C connection. By default we set it to 1 which will cause the initialization to fail when the register update fails. More...

bool	mtb_wm8960_init (uint8_t features)
	Initialize the I2C communication with the audio codec, reset the codec and apply default configuration based on the feature(s) requested. More...

void	mtb_wm8960_free ()
	Frees up any resources allocated by the driver as part of mtb_wm8960_init().

bool	mtb_wm8960_adjust_input_volume (uint8_t volume)
	This function updates the volume of both the left and right channels of the microphone input. More...

bool	mtb_wm8960_adjust_heaphone_output_volume (uint8_t volume)
	This function updates the volume of both the left and right channels of the headphone output. More...

bool	mtb_wm8960_adjust_speaker_output_volume (uint8_t volume)
	This function updates the volume of both the left and right channels of the speaker output. More...

bool	mtb_wm8960_set_output_volume (uint8_t volume)
	This function updates the volume of both the left and right channels of the speaker and headphones. More...

bool	mtb_wm8960_activate (void)
	This function powers up the modules the required for the features enabled using mtb_wm8960_init. This function is called in conjunction with mtb_wm8960_deactivate. More...

bool	mtb_wm8960_deactivate (void)
	This function powers down the modules the required for the features enabled using mtb_wm8960_init. More...

bool	mtb_wm8960_read (mtb_wm8960_reg_t reg, uint16_t *data)
	This function reads value of an audio codec register. More...

bool	mtb_wm8960_write (mtb_wm8960_reg_t reg, uint16_t data)
	This function writes data to an audio codec register. More...

bool	mtb_wm8960_set (mtb_wm8960_reg_t reg, uint16_t mask)
	This function sets bits in a register. This function can be used instead of mtb_wm8960_write() if you want to change a single bit or select bits in the register and preserve the value of other bits in the register. Only the bits set to 1 in the mask are affected. More...

bool	mtb_wm8960_clear (mtb_wm8960_reg_t reg, uint16_t mask)
	This function clears bits in a register. This function can be used instead of mtb_wm8960_write() if you want to change a single bit or select bits in the register and preserve the value of other bits in the register. Only the bits set to 1 in the mask are affected. More...

bool	mtb_wm8960_configure_clocking (uint32_t mclk_hz, bool enable_pll, mtb_wm8960_adc_dac_sample_rate_t sample_rate, mtb_wm8960_word_length_t word_length, mtb_wm8960_mode_t mode)
	This function configures the master clock and the digital interface for the audio codec. More...

bool	mtb_wm8960_dump ()
	This function dumps the actual register values. More...

bool	i2c_write (uint8_t address, uint8_t data[2])

Detailed Description

Description: This file contains the function prototypes and constants used in mtb_wm8960.c. This driver is intended for the WM8960 audio codec.

Copyright: Copyright 2018-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Macro Definition Documentation

◆ MTB_RSLT_WM8960_BAD_ARG

#define MTB_RSLT_WM8960_BAD_ARG false

Invalid argument was passed into a function.

◆ WM8960_3D_CTR_3DDEPTH_100

#define WM8960_3D_CTR_3DDEPTH_100 0x01Eu

3D Stereo Depth 100%

◆ WM8960_3D_CTR_3DEN

#define WM8960_3D_CTR_3DEN 0x001u

3D Stereo Enhancement Enable

◆ WM8960_3D_CTR_3DLC_HIGH

#define WM8960_3D_CTR_3DLC_HIGH 0x020u

3D Enhance Filter Lower Cut-Off Frequency High (Recommended for fs<32kHz)

◆ WM8960_3D_CTR_3DLC_LOW

#define WM8960_3D_CTR_3DLC_LOW 0x000u

3D Enhance Filter Lower Cut-Off Frequency Low (Recommended for fs>=32kHz)

◆ WM8960_3D_CTR_3DUC_HIGH

#define WM8960_3D_CTR_3DUC_HIGH 0x000u

3D Enhance Filter Upper Cut-Off Frequency High (Recommended for fs>=32kHz)

◆ WM8960_3D_CTR_3DUC_LOW

#define WM8960_3D_CTR_3DUC_LOW 0x040u

3D Enhance Filter Upper Cut-Off Frequency Low (Recommended for fs<32kHz)

◆ WM8960_ADCL_ADCR_SIG_PTH_MIC2B_CON

#define WM8960_ADCL_ADCR_SIG_PTH_MIC2B_CON 0x008u

Connect I/P PGA to I/P Boost Mixer

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_0dB

#define WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_0dB 0x000u

Input PGA Boost Gain 0dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_13dB

#define WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_13dB 0x010u

Input PGA Boost Gain 13dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_20dB

#define WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_20dB 0x020u

Input PGA Boost Gain 20dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_29dB

#define WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_29dB 0x030u

Input PGA Boost Gain 29dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MN1_CON

#define WM8960_ADCL_ADCR_SIG_PTH_MN1_CON 0x100u

Connect (L/R)INPUT1 to inverting input of Input PGA

◆ WM8960_ADCL_ADCR_SIG_PTH_MP2_CON

#define WM8960_ADCL_ADCR_SIG_PTH_MP2_CON 0x040u

Connect (L/R)INPUT2 to non-inverting input of Input PGA

◆ WM8960_ADCL_ADCR_SIG_PTH_MP3_CON

#define WM8960_ADCL_ADCR_SIG_PTH_MP3_CON 0x080u

Connect (L/R)INPUT3 to non-inverting input of Input PGA

◆ WM8960_AUDIO_INTF0_ALRSWAP

#define WM8960_AUDIO_INTF0_ALRSWAP 0x100u

Left/Right ADC Channel Swap. Swap left and right ADC data in audio interface

◆ WM8960_AUDIO_INTF0_BCLKINV

#define WM8960_AUDIO_INTF0_BCLKINV 0x080u

BCLK invert bit. BCLK inverted

◆ WM8960_AUDIO_INTF0_DLRSWAP

#define WM8960_AUDIO_INTF0_DLRSWAP 0x020u

Left/Right DAC Channel Swap. Swap left and right DAC data in audio interface

◆ WM8960_AUDIO_INTF0_FORMAT_DSP_MODE

#define WM8960_AUDIO_INTF0_FORMAT_DSP_MODE 0x003u

DSP Mode

◆ WM8960_AUDIO_INTF0_FORMAT_I2S_MODE

#define WM8960_AUDIO_INTF0_FORMAT_I2S_MODE 0x002u

I2S format

◆ WM8960_AUDIO_INTF0_FORMAT_L_JUSTIF

#define WM8960_AUDIO_INTF0_FORMAT_L_JUSTIF 0x001u

Left justified format

◆ WM8960_AUDIO_INTF0_FORMAT_R_JUSTIF

#define WM8960_AUDIO_INTF0_FORMAT_R_JUSTIF 0x000u

Right justified format

◆ WM8960_AUDIO_INTF0_LRP_INV

#define WM8960_AUDIO_INTF0_LRP_INV 0x010u

Right, left and I2S modes – LRCLK polarity. Invert LRCLK polarity

◆ WM8960_AUDIO_INTF0_MS_MASTER

#define WM8960_AUDIO_INTF0_MS_MASTER 0x040u

Master Mode.

◆ WM8960_AUDIO_INTF0_MS_SLAVE

#define WM8960_AUDIO_INTF0_MS_SLAVE 0x000u

Slave Mode.

◆ WM8960_AUDIO_INTF0_WL_16BITS

#define WM8960_AUDIO_INTF0_WL_16BITS 0x000u

Audio Data Word Length. 16 bits

◆ WM8960_AUDIO_INTF0_WL_20BITS

#define WM8960_AUDIO_INTF0_WL_20BITS 0x004u

Audio Data Word Length. 20 bits

◆ WM8960_AUDIO_INTF0_WL_24BITS

#define WM8960_AUDIO_INTF0_WL_24BITS 0x008u

Audio Data Word Length. 24 bits

◆ WM8960_AUDIO_INTF0_WL_32BITS

#define WM8960_AUDIO_INTF0_WL_32BITS 0x00Cu

Audio Data Word Length. 32 bits

◆ WM8960_AUDIO_INTF1_ADCCOMP_ALAW

#define WM8960_AUDIO_INTF1_ADCCOMP_ALAW 0x006u

ADC companding. A-Law

◆ WM8960_AUDIO_INTF1_ADCCOMP_ULAW

#define WM8960_AUDIO_INTF1_ADCCOMP_ULAW 0x004u

ADC companding. u-Law

◆ WM8960_AUDIO_INTF1_ALRCGPIO_GPIO

#define WM8960_AUDIO_INTF1_ALRCGPIO_GPIO 0x040u

GPIO1 Pin Function Select

◆ WM8960_AUDIO_INTF1_DACCOMP_ALAW

#define WM8960_AUDIO_INTF1_DACCOMP_ALAW 0x010u

DAC companding. A-Law

◆ WM8960_AUDIO_INTF1_DACCOMP_ULAW

#define WM8960_AUDIO_INTF1_DACCOMP_ULAW 0x018u

DAC companding. u-Law

◆ WM8960_AUDIO_INTF1_LOOPBACK_EN

#define WM8960_AUDIO_INTF1_LOOPBACK_EN 0x001u

Loopback enabled, ADC data output is fed directly into DAC data input.

◆ WM8960_AUDIO_INTF1_WL8_8BIT

#define WM8960_AUDIO_INTF1_WL8_8BIT 0x020u

8-Bit Word Length Select. Device operates in 8-bit mode.

◆ WM8960_CLK1_ADCDIV_BY_1

#define WM8960_CLK1_ADCDIV_BY_1 0x000u

ADC Sample rate divider (SYSCLK/(1 * 256))

◆ WM8960_CLK1_ADCDIV_BY_1_5

#define WM8960_CLK1_ADCDIV_BY_1_5 0x040u

ADC Sample rate divider (SYSCLK/(1.5 * 256))

◆ WM8960_CLK1_ADCDIV_BY_2

#define WM8960_CLK1_ADCDIV_BY_2 0x080u

ADC Sample rate divider (SYSCLK/(2 * 256))

◆ WM8960_CLK1_ADCDIV_BY_3

#define WM8960_CLK1_ADCDIV_BY_3 0x0C0u

ADC Sample rate divider (SYSCLK/(3 * 256))

◆ WM8960_CLK1_ADCDIV_BY_4

#define WM8960_CLK1_ADCDIV_BY_4 0x100u

ADC Sample rate divider (SYSCLK/(4 * 256))

◆ WM8960_CLK1_ADCDIV_BY_5_5

#define WM8960_CLK1_ADCDIV_BY_5_5 0x140u

ADC Sample rate divider (SYSCLK/(5.5 * 256))

◆ WM8960_CLK1_ADCDIV_BY_6

#define WM8960_CLK1_ADCDIV_BY_6 0x180u

ADC Sample rate divider (SYSCLK/(6 * 256))

◆ WM8960_CLK1_CLKSEL_MCLK

#define WM8960_CLK1_CLKSEL_MCLK 0x000u

SYSCLK derived from MCLK

◆ WM8960_CLK1_CLKSEL_PLL

#define WM8960_CLK1_CLKSEL_PLL 0x001u

SYSCLK derived from PLL output

◆ WM8960_CLK1_DACDIV_BY_1

#define WM8960_CLK1_DACDIV_BY_1 0x000u

DAC Sample rate divider (SYSCLK/(1 * 256))

◆ WM8960_CLK1_DACDIV_BY_1_5

#define WM8960_CLK1_DACDIV_BY_1_5 0x008u

DAC Sample rate divider (SYSCLK/(1.5 * 256))

◆ WM8960_CLK1_DACDIV_BY_2

#define WM8960_CLK1_DACDIV_BY_2 0x010u

DAC Sample rate divider (SYSCLK/(2 * 256))

◆ WM8960_CLK1_DACDIV_BY_3

#define WM8960_CLK1_DACDIV_BY_3 0x018u

DAC Sample rate divider (SYSCLK/(3 * 256))

◆ WM8960_CLK1_DACDIV_BY_4

#define WM8960_CLK1_DACDIV_BY_4 0x020u

DAC Sample rate divider (SYSCLK/(4 * 256))

◆ WM8960_CLK1_DACDIV_BY_5_5

#define WM8960_CLK1_DACDIV_BY_5_5 0x028u

DAC Sample rate divider (SYSCLK/(5.5 * 256))

◆ WM8960_CLK1_DACDIV_BY_6

#define WM8960_CLK1_DACDIV_BY_6 0x030u

DAC Sample rate divider (SYSCLK/(6 * 256))

◆ WM8960_CLK1_SYSCLKDIV_BY_1

#define WM8960_CLK1_SYSCLKDIV_BY_1 0x000u

SYSCLK Pre-divider. Divide SYSCLK by 1

◆ WM8960_CLK1_SYSCLKDIV_BY_2

#define WM8960_CLK1_SYSCLKDIV_BY_2 0x004u

SYSCLK Pre-divider. Divide SYSCLK by 2

◆ WM8960_CLK2_BCLKDIV_BY_11

#define WM8960_CLK2_BCLKDIV_BY_11 0x008u

BCLK Frequency (SYSCLK/11)

◆ WM8960_CLK2_BCLKDIV_BY_12

#define WM8960_CLK2_BCLKDIV_BY_12 0x009u

BCLK Frequency (SYSCLK/12)

◆ WM8960_CLK2_BCLKDIV_BY_16

#define WM8960_CLK2_BCLKDIV_BY_16 0x00Au

BCLK Frequency (SYSCLK/16)

◆ WM8960_CLK2_BCLKDIV_BY_1_5

#define WM8960_CLK2_BCLKDIV_BY_1_5 0x001u

BCLK Frequency (SYSCLK/1.5)

◆ WM8960_CLK2_BCLKDIV_BY_2

#define WM8960_CLK2_BCLKDIV_BY_2 0x002u

BCLK Frequency (SYSCLK/2)

◆ WM8960_CLK2_BCLKDIV_BY_22

#define WM8960_CLK2_BCLKDIV_BY_22 0x00Bu

BCLK Frequency (SYSCLK/22)

◆ WM8960_CLK2_BCLKDIV_BY_24

#define WM8960_CLK2_BCLKDIV_BY_24 0x00Cu

BCLK Frequency (SYSCLK/24)

◆ WM8960_CLK2_BCLKDIV_BY_3

#define WM8960_CLK2_BCLKDIV_BY_3 0x003u

BCLK Frequency (SYSCLK/3)

◆ WM8960_CLK2_BCLKDIV_BY_32

#define WM8960_CLK2_BCLKDIV_BY_32 0x00Du

BCLK Frequency (SYSCLK/32)

◆ WM8960_CLK2_BCLKDIV_BY_4

#define WM8960_CLK2_BCLKDIV_BY_4 0x004u

BCLK Frequency (SYSCLK/4)

◆ WM8960_CLK2_BCLKDIV_BY_5_5

#define WM8960_CLK2_BCLKDIV_BY_5_5 0x005u

BCLK Frequency (SYSCLK/5.5)

◆ WM8960_CLK2_BCLKDIV_BY_6

#define WM8960_CLK2_BCLKDIV_BY_6 0x006u

BCLK Frequency (SYSCLK/6)

◆ WM8960_CLK2_BCLKDIV_BY_8

#define WM8960_CLK2_BCLKDIV_BY_8 0x007u

BCLK Frequency (SYSCLK/8)

◆ WM8960_CLK2_DCLKDIV_BY_12

#define WM8960_CLK2_DCLKDIV_BY_12 0x180u

Class D switching clock divider (SYSCLK/12)

◆ WM8960_CLK2_DCLKDIV_BY_16

#define WM8960_CLK2_DCLKDIV_BY_16 0x1C0u

Class D switching clock divider (SYSCLK/16)

◆ WM8960_CLK2_DCLKDIV_BY_2

#define WM8960_CLK2_DCLKDIV_BY_2 0x040u

Class D switching clock divider (SYSCLK/2)

◆ WM8960_CLK2_DCLKDIV_BY_3

#define WM8960_CLK2_DCLKDIV_BY_3 0x080u

Class D switching clock divider (SYSCLK/3)

◆ WM8960_CLK2_DCLKDIV_BY_4

#define WM8960_CLK2_DCLKDIV_BY_4 0x0C0u

Class D switching clock divider (SYSCLK/4)

◆ WM8960_CLK2_DCLKDIV_BY_6

#define WM8960_CLK2_DCLKDIV_BY_6 0x100u

Class D switching clock divider (SYSCLK/6)

◆ WM8960_CLK2_DCLKDIV_BY_8

#define WM8960_CLK2_DCLKDIV_BY_8 0x140u

Class D switching clock divider (SYSCLK/8)

◆ WM8960_CTR1_ADCHPD_DIS

#define WM8960_CTR1_ADCHPD_DIS 0x001u

ADC High Pass Filter Disable

◆ WM8960_CTR1_ADCPOL_L_INV

#define WM8960_CTR1_ADCPOL_L_INV 0x040u

ADC polarity control. ADC R inverted

◆ WM8960_CTR1_ADCPOL_LR_INV

#define WM8960_CTR1_ADCPOL_LR_INV 0x060u

ADC polarity control. ADC L and R inverted

◆ WM8960_CTR1_ADCPOL_R_INV

#define WM8960_CTR1_ADCPOL_R_INV 0x020u

ADC polarity control. ADC L inverted

◆ WM8960_CTR1_DACDIV2_6B_EN

#define WM8960_CTR1_DACDIV2_6B_EN 0x080u

DAC 6dB Attenuate Enable,

◆ WM8960_CTR1_DACMU_MUTE

#define WM8960_CTR1_DACMU_MUTE 0x008u

DAC Digital Soft Mute enabled

◆ WM8960_CTR1_DACMU_NO

#define WM8960_CTR1_DACMU_NO 0x000u

DAC Digital Soft Mute disabled

◆ WM8960_CTR1_DEEMPH_32_KHZ

#define WM8960_CTR1_DEEMPH_32_KHZ 0x002u

De-emphasis Control for 32 KHz sample rate

◆ WM8960_CTR1_DEEMPH_44_1_KHZ

#define WM8960_CTR1_DEEMPH_44_1_KHZ 0x004u

De-emphasis Control for 44.1 KHz sample rate

◆ WM8960_CTR1_DEEMPH_48_KHZ

#define WM8960_CTR1_DEEMPH_48_KHZ 0x006u

De-emphasis Control for 48 KHz sample rate

◆ WM8960_CTR2_DACMR_SLOW_RMP

#define WM8960_CTR2_DACMR_SLOW_RMP 0x004u

DAC Soft Mute Ramp Rate. Slow ramp (1.5kHz at fs=48k, providing maximum delay of 171ms)

◆ WM8960_CTR2_DACPOL_L_INV

#define WM8960_CTR2_DACPOL_L_INV 0x040u

DAC polarity control. DAC R inverted

◆ WM8960_CTR2_DACPOL_LR_INV

#define WM8960_CTR2_DACPOL_LR_INV 0x060u

DAC polarity control. DAC L and R inverted

◆ WM8960_CTR2_DACPOL_R_INV

#define WM8960_CTR2_DACPOL_R_INV 0x020u

DAC polarity control. DAC L inverted

◆ WM8960_CTR2_DACSLOPE_SS

#define WM8960_CTR2_DACSLOPE_SS 0x002u

DAC filter characteristics. Sloping stopband

◆ WM8960_CTR2_DACSMM_GRAD

#define WM8960_CTR2_DACSMM_GRAD 0x008u

DAC Soft Mute Mode. Disabling soft-mute (DACMU=0) will cause the volume to ramp up gradually to the LDACVOL/RDACVOL settings

◆ WM8960_I2C_ADDRESS

#define WM8960_I2C_ADDRESS (0x1A)

Basic set of APIs for interacting with the WM8960 audio codec display. This provides basic initialization and access to to the audio codec.

◆ WM8960_LEFT_OUT_MIX_LD2LO_EN

#define WM8960_LEFT_OUT_MIX_LD2LO_EN 0x100u

< Connect Left DAC to Left Output Mixer

◆ WM8960_LEFT_OUT_MIX_LI2LO_EN

#define WM8960_LEFT_OUT_MIX_LI2LO_EN 0x080u

Connect LINPUT3 to Left Output Mixer

◆ WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_0dB

#define WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_0dB 0x0C3u

ADC Volume Control 0dB

◆ WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_30dB

#define WM8960_LEFT_RIGHT_ADC_VOL_ADCVOL_30dB 0x0FFu

DAC Volume Control 30dB

◆ WM8960_LEFT_RIGHT_ADC_VOL_ADCVU_UP

#define WM8960_LEFT_RIGHT_ADC_VOL_ADCVU_UP 0x100u

ADC Volume Update bit

◆ WM8960_LEFT_RIGHT_DAC_VOL_0dB

#define WM8960_LEFT_RIGHT_DAC_VOL_0dB 0x0FFu

DAC Volume Control 0dB

◆ WM8960_LEFT_RIGHT_DAC_VOL_127dB

#define WM8960_LEFT_RIGHT_DAC_VOL_127dB 0x001u

DAC Volume Control -127dB

◆ WM8960_LEFT_RIGHT_DAC_VOL_DACVU_UP

#define WM8960_LEFT_RIGHT_DAC_VOL_DACVU_UP 0x100u

DAC Volume Update bit

◆ WM8960_LEFT_RIGHT_IN_VOL_INMUTE

#define WM8960_LEFT_RIGHT_IN_VOL_INMUTE 0x080u

Input PGA Analogue Mute

◆ WM8960_LEFT_RIGHT_IN_VOL_INVOL_0dB

#define WM8960_LEFT_RIGHT_IN_VOL_INVOL_0dB 0x017u

Input PGA Volume 0dB

◆ WM8960_LEFT_RIGHT_IN_VOL_INVOL_30dB

#define WM8960_LEFT_RIGHT_IN_VOL_INVOL_30dB 0x03Fu

Input PGA Volume 30dB

◆ WM8960_LEFT_RIGHT_IN_VOL_IPVU

#define WM8960_LEFT_RIGHT_IN_VOL_IPVU 0x100u

Input PGA Volume Update

◆ WM8960_LEFT_RIGHT_IN_VOL_IZC_ZC

#define WM8960_LEFT_RIGHT_IN_VOL_IZC_ZC 0x040u

Input PGA Zero Cross Detector

◆ WM8960_LOUT1_ROUT1_VOL_O1ZC_ZC

#define WM8960_LOUT1_ROUT1_VOL_O1ZC_ZC 0x080u

Headphone Output Zero Cross Enable

◆ WM8960_LOUT1_ROUT1_VOL_OUT1VOL_0dB

#define WM8960_LOUT1_ROUT1_VOL_OUT1VOL_0dB 0x079u

LOUT1 or ROUT1 Volume 0dB

◆ WM8960_LOUT1_ROUT1_VOL_OUT1VOL_6dB

#define WM8960_LOUT1_ROUT1_VOL_OUT1VOL_6dB 0x07Fu

LOUT1 or ROUT1 Volume 6dB

◆ WM8960_LOUT1_ROUT1_VOL_OUT1VU

#define WM8960_LOUT1_ROUT1_VOL_OUT1VU 0x100u

Headphone Output Volume Update

◆ WM8960_LOUT2_ROUT2_VOL_SPKRVOL_0dB

#define WM8960_LOUT2_ROUT2_VOL_SPKRVOL_0dB 0x079u

SPK_RP/SPK_RN Volume 0dB

◆ WM8960_LOUT2_ROUT2_VOL_SPKRVOL_6dB

#define WM8960_LOUT2_ROUT2_VOL_SPKRVOL_6dB 0x07Fu

SPK_RP/SPK_RN Volume 6dB

◆ WM8960_LOUT2_ROUT2_VOL_SPKRZC

#define WM8960_LOUT2_ROUT2_VOL_SPKRZC 0x080u

Speaker Zero Cross Enable

◆ WM8960_LOUT2_ROUT2_VOL_SPKVU

#define WM8960_LOUT2_ROUT2_VOL_SPKVU 0x100u

Speaker Volume Update

◆ WM8960_MONO_OUT_MIX1_MIX2_2MO_DI

#define WM8960_MONO_OUT_MIX1_MIX2_2MO_DI 0x000u

Disconnect Left Output Mixer to Mono Output Mixer Control

◆ WM8960_MONO_OUT_MIX1_MIX2_2MO_EN

#define WM8960_MONO_OUT_MIX1_MIX2_2MO_EN 0x080u

Connect Right Output Mixer to Mono Output Mixer Control

◆ WM8960_PLL_N_OPCLKDIV_BY_1

#define WM8960_PLL_N_OPCLKDIV_BY_1 0x000u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK)

◆ WM8960_PLL_N_OPCLKDIV_BY_2

#define WM8960_PLL_N_OPCLKDIV_BY_2 0x040u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK/2)

◆ WM8960_PLL_N_OPCLKDIV_BY_3

#define WM8960_PLL_N_OPCLKDIV_BY_3 0x080u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK/3)

◆ WM8960_PLL_N_OPCLKDIV_BY_4

#define WM8960_PLL_N_OPCLKDIV_BY_4 0x0C0u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK/4)

◆ WM8960_PLL_N_OPCLKDIV_BY_5_5

#define WM8960_PLL_N_OPCLKDIV_BY_5_5 0x100u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK/5.5)

◆ WM8960_PLL_N_OPCLKDIV_BY_6

#define WM8960_PLL_N_OPCLKDIV_BY_6 0x140u

SYSCLK Output to GPIO Clock Division ratio. (SYSCLK/6)

◆ WM8960_PLL_N_PLLPRESCALE_DI

#define WM8960_PLL_N_PLLPRESCALE_DI 0x000u

MCLK input directly into PLL

◆ WM8960_PLL_N_PLLPRESCALE_EN

#define WM8960_PLL_N_PLLPRESCALE_EN 0x010u

Divide MCLK by 2 before input to PLL

◆ WM8960_PLL_N_SDM_FRAC

#define WM8960_PLL_N_SDM_FRAC 0x020u

Enable Fractional Mode

◆ WM8960_PLL_N_SDM_INT

#define WM8960_PLL_N_SDM_INT 0x000u

Enable Integer Mode

◆ WM8960_PWR_MGMT1_ADCL_UP

#define WM8960_PWR_MGMT1_ADCL_UP 0x008u

ADC Left power up

◆ WM8960_PWR_MGMT1_ADCR_UP

#define WM8960_PWR_MGMT1_ADCR_UP 0x004u

ADC Right power up

◆ WM8960_PWR_MGMT1_AINL_UP

#define WM8960_PWR_MGMT1_AINL_UP 0x020u

Analogue in PGA Left power up

◆ WM8960_PWR_MGMT1_AINR_UP

#define WM8960_PWR_MGMT1_AINR_UP 0x010u

Analogue in PGA Right power up

◆ WM8960_PWR_MGMT1_DIGENB_DI

#define WM8960_PWR_MGMT1_DIGENB_DI 0x001u

Master Clock disabled

◆ WM8960_PWR_MGMT1_MICB_UP

#define WM8960_PWR_MGMT1_MICB_UP 0x002u

MICBIAS power up

◆ WM8960_PWR_MGMT1_VMIDSEL_250K

#define WM8960_PWR_MGMT1_VMIDSEL_250K 0x100u

2 x 250k Divider enabled (for low-power standby)

◆ WM8960_PWR_MGMT1_VMIDSEL_50K

#define WM8960_PWR_MGMT1_VMIDSEL_50K 0x080u

2 x 50k Divider enabled (for playback/record)

◆ WM8960_PWR_MGMT1_VMIDSEL_5K

#define WM8960_PWR_MGMT1_VMIDSEL_5K 0x180u

2 x 5k Divider enabled (for fast start-up)

◆ WM8960_PWR_MGMT1_VREF_UP

#define WM8960_PWR_MGMT1_VREF_UP 0x040u

VREF power up

◆ WM8960_PWR_MGMT2_DACL_UP

#define WM8960_PWR_MGMT2_DACL_UP 0x100u

DAC Left power up

◆ WM8960_PWR_MGMT2_DACR_UP

#define WM8960_PWR_MGMT2_DACR_UP 0x080u

DAC Right power up

◆ WM8960_PWR_MGMT2_LOUT1_UP

#define WM8960_PWR_MGMT2_LOUT1_UP 0x040u

LOUT1 Output Buffer power up

◆ WM8960_PWR_MGMT2_OUT3_UP

#define WM8960_PWR_MGMT2_OUT3_UP 0x002u

OUT3 Output Buffer power up

◆ WM8960_PWR_MGMT2_PLL_EN_UP

#define WM8960_PWR_MGMT2_PLL_EN_UP 0x001u

PLL power up

◆ WM8960_PWR_MGMT2_ROUT1_UP

#define WM8960_PWR_MGMT2_ROUT1_UP 0x020u

ROUT1 Output Buffer power up

◆ WM8960_PWR_MGMT2_SPKL_UP

#define WM8960_PWR_MGMT2_SPKL_UP 0x010u

SPK_LP/SPK_LN Output Buffers power up

◆ WM8960_PWR_MGMT2_SPKR_UP

#define WM8960_PWR_MGMT2_SPKR_UP 0x008u

SPK_RP/SPK_RN Output Buffers power up

◆ WM8960_PWR_MGMT3_LMIC_UP

#define WM8960_PWR_MGMT3_LMIC_UP 0x020u

Left Channel Input PGA Enable

◆ WM8960_PWR_MGMT3_LOMIX_UP

#define WM8960_PWR_MGMT3_LOMIX_UP 0x008u

Left Output Mixer Enable

◆ WM8960_PWR_MGMT3_RMIC_UP

#define WM8960_PWR_MGMT3_RMIC_UP 0x010u

Right Channel Input PGA Enable

◆ WM8960_PWR_MGMT3_ROMIX_UP

#define WM8960_PWR_MGMT3_ROMIX_UP 0x004u

Right Output Mixer Enable

◆ WM8960_RIGHT_OUT_MIX_RD2RO_EN

#define WM8960_RIGHT_OUT_MIX_RD2RO_EN 0x100u

Connect Right DAC to Right Output Mixer

◆ WM8960_RIGHT_OUT_MIX_RI2RO_EN

#define WM8960_RIGHT_OUT_MIX_RI2RO_EN 0x080u

Connect RINPUT3 to Right Output Mixer

Enumeration Type Documentation

◆ mtb_wm8960_adc_dac_sample_rate_t

enum mtb_wm8960_adc_dac_sample_rate_t

Enumeration for supported sample rates for ADC and DAC in the WM8960 audio codec.

Enumerator
WM8960_ADC_DAC_SAMPLE_RATE_48_KHZ	48 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_44_1_KHZ	44.1 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_32_KHZ	32 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_24_KHZ	24 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_22_05_KHZ	22.05 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_16_KHZ	16 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_12_KHZ	12 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_11_025_KHZ	11.025 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_8_018_KHZ	8.018 KHz sample rate
WM8960_ADC_DAC_SAMPLE_RATE_8_KHZ	8 KHz sample rate

◆ mtb_wm8960_features_t

enum mtb_wm8960_features_t

Enumeration of bit flags enabling/disabling features of the WM8960 audio codec.

Note: The values of the enumeration can be OR'ed to enable multiple features

Enumerator
WM8960_FEATURE_NONE	No features enabled
WM8960_FEATURE_MICROPHONE	Enable the microphone
WM8960_FEATURE_HEADPHONE	Enable the headphone
WM8960_FEATURE_SPEAKER	Enable the class D speaker

◆ mtb_wm8960_mode_t

enum mtb_wm8960_mode_t

Enumeration to select mode of operation of the WM8960 audio codec.

Enumerator
WM8960_MODE_MASTER	Master mode
WM8960_MODE_SLAVE	Slave mode

◆ mtb_wm8960_reg_t

enum mtb_wm8960_reg_t

Enumeration for the WM8960 I2C Interface Register Addresses

The entries below are intended for use with these functions:

Enumerator
WM8960_REG_LEFT_IN_VOL	0x00: Left Input volume
WM8960_REG_RIGHT_IN_VOL	0x01: Right Input volume
WM8960_REG_LOUT1_VOL	0x02: LOUT1 volume
WM8960_REG_ROUT1_VOL	0x03: ROUT1 volume
WM8960_REG_CLK1	0x04: Clocking (1)
WM8960_REG_CTR1	0x05: ADC & DAC Control (CTR1)
WM8960_REG_CTR2	0x06: ADC & DAC Control (CTR2)
WM8960_REG_AUDIO_INTF0	0x07: Audio Interface (0)
WM8960_REG_CLK2	0x08: Clocking (2)
WM8960_REG_AUDIO_INTF1	0x09: Audio Interface (1)
WM8960_REG_LEFT_DAC_VOL	0x0A: Left DAC volume
WM8960_REG_RIGHT_DAC_VOL	0x0B: Right DAC volume
WM8960_REG_RESET	0x0F: Reset
WM8960_REG_3D_CTR	0x10: 3D Control
WM8960_REG_ALC1	0x11: ALC1
WM8960_REG_ALC2	0x12: ALC2
WM8960_REG_ALC3	0x13: ALC3
WM8960_REG_NOISE_GATE	0x14: Noise Gate
WM8960_REG_LEFT_ADC_VOL	0x15: Left ADC volume
WM8960_REG_RIGHT_ADC_VOL	0x16: Right ADC volume
WM8960_REG_ADD_CTL1	0x17: Additional Control (1)
WM8960_REG_ADD_CTL2	0x18: Additional Control (2)
WM8960_REG_PWR_MGMT1	0x19: Power Management (1)
WM8960_REG_PWR_MGMT2	0x1A: Power Management (2)
WM8960_REG_ADD_CTL3	0x1B: Additional Control (3)
WM8960_REG_ANTI_POP1	0x1C: Anti-pop 1
WM8960_REG_ANTI_POP2	0x1D: Anti-pop 2
WM8960_REG_ADCL_SIG_PTH	0x20: ADCL signal path
WM8960_REG_ADCR_SIG_PTH	0x21: ADCR signal path
WM8960_REG_LEFT_OUT_MIX	0x22: Left out Mix (1)
WM8960_REG_RIGHT_OUT_MIX	0x25: Right out Mix (2)
WM8960_REG_MONO_OUT_MIX1	0x26: Mono out Mix (1)
WM8960_REG_MONO_OUT_MIX2	0x27: Mono out Mix (2)
WM8960_REG_LOUT2_VOL	0x28: LOUT2 volume
WM8960_REG_ROUT2_VOL	0x29: ROUT2 volume
WM8960_REG_MONO_OUT_VOL	0x2A: Mono out volume
WM8960_REG_IN_BOOST_MIX1	0x2B: Input boost mixer (1)
WM8960_REG_IN_BOOST_MIX2	0x2C: Input boost mixer (2)
WM8960_REG_BYPASS1	0x2D: Bypass (1)
WM8960_REG_BYPASS2	0x2E: Bypass (2)
WM8960_REG_PWR_MGMT3	0x2F: Power Management (3)
WM8960_REG_ADD_CTL4	0x30: Additional Control (4)
WM8960_REG_CLASS_D_CTL1	0x31: Class D Control (1)
WM8960_REG_CLASS_D_CTL3	0x33: Class D Control (3)
WM8960_REG_PLL_N	0x34: PLL N
WM8960_REG_PLL_K1	0x35: PLL K 1
WM8960_REG_PLL_K2	0x36: PLL K 2
WM8960_REG_PLL_K3	0x37: PLL K 3

◆ mtb_wm8960_word_length_t

enum mtb_wm8960_word_length_t

Enumeration for supported word lengths in the WM8960 audio codec.

Enumerator
WM8960_WL_16BITS	16-bit word length
WM8960_WL_20BITS	20-bit word length
WM8960_WL_24BITS	24-bit word length
WM8960_WL_32BITS	32-bit word length

Function Documentation

◆ i2c_write()

bool i2c_write	(	uint8_t	address,
		uint8_t	data[2]
	)

Platform dependent i2c write. If you compile this library outside of Arduino you need to provide your own implementation.

◆ mtb_wm8960_clear()

bool mtb_wm8960_clear	(	mtb_wm8960_reg_t	reg,
		uint16_t	mask
	)

This function clears bits in a register. This function can be used instead of mtb_wm8960_write() if you want to change a single bit or select bits in the register and preserve the value of other bits in the register. Only the bits set to 1 in the mask are affected.

Parameters

[in]	reg	The audio codec register to update
[in]	mask	The mask used to clear bits in the register

Returns: true if properly initialized, else an error indicating what went wrong.

◆ mtb_wm8960_read()

bool mtb_wm8960_read	(	mtb_wm8960_reg_t	reg,
		uint16_t *	data
	)

This function reads value of an audio codec register.

Parameters

[in]	reg	The audio codec register to read
[out]	data	The reference to read the audio codec register data into.

Returns: true if properly initialized, else an error indicating what went wrong.

◆ mtb_wm8960_set()

bool mtb_wm8960_set	(	mtb_wm8960_reg_t	reg,
		uint16_t	mask
	)

This function sets bits in a register. This function can be used instead of mtb_wm8960_write() if you want to change a single bit or select bits in the register and preserve the value of other bits in the register. Only the bits set to 1 in the mask are affected.

Parameters

[in]	reg	The audio codec register to update
[in]	mask	The mask used to set bits in the register

Returns: true if properly initialized, else an error indicating what went wrong.

◆ mtb_wm8960_write()

bool mtb_wm8960_write	(	mtb_wm8960_reg_t	reg,
		uint16_t	data
	)

This function writes data to an audio codec register.

Parameters

[in]	reg	The audio codec register to update
[in]	data	The data to be written to the audio codec register

Returns: true if properly initialized, else an error indicating what went wrong.

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ MTB_RSLT_WM8960_BAD_ARG

◆ WM8960_3D_CTR_3DDEPTH_100

◆ WM8960_3D_CTR_3DEN

◆ WM8960_3D_CTR_3DLC_HIGH

◆ WM8960_3D_CTR_3DLC_LOW

◆ WM8960_3D_CTR_3DUC_HIGH

◆ WM8960_3D_CTR_3DUC_LOW

◆ WM8960_ADCL_ADCR_SIG_PTH_MIC2B_CON

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_0dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_13dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_20dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MICBOOST_29dB

◆ WM8960_ADCL_ADCR_SIG_PTH_MN1_CON

◆ WM8960_ADCL_ADCR_SIG_PTH_MP2_CON

◆ WM8960_ADCL_ADCR_SIG_PTH_MP3_CON

◆ WM8960_AUDIO_INTF0_ALRSWAP

◆ WM8960_AUDIO_INTF0_BCLKINV

◆ WM8960_AUDIO_INTF0_DLRSWAP

◆ WM8960_AUDIO_INTF0_FORMAT_DSP_MODE

◆ WM8960_AUDIO_INTF0_FORMAT_I2S_MODE

◆ WM8960_AUDIO_INTF0_FORMAT_L_JUSTIF

◆ WM8960_AUDIO_INTF0_FORMAT_R_JUSTIF

◆ WM8960_AUDIO_INTF0_LRP_INV

◆ WM8960_AUDIO_INTF0_MS_MASTER

◆ WM8960_AUDIO_INTF0_MS_SLAVE

◆ WM8960_AUDIO_INTF0_WL_16BITS

◆ WM8960_AUDIO_INTF0_WL_20BITS

◆ WM8960_AUDIO_INTF0_WL_24BITS

◆ WM8960_AUDIO_INTF0_WL_32BITS

◆ WM8960_AUDIO_INTF1_ADCCOMP_ALAW

◆ WM8960_AUDIO_INTF1_ADCCOMP_ULAW

◆ WM8960_AUDIO_INTF1_ALRCGPIO_GPIO

◆ WM8960_AUDIO_INTF1_DACCOMP_ALAW

◆ WM8960_AUDIO_INTF1_DACCOMP_ULAW

◆ WM8960_AUDIO_INTF1_LOOPBACK_EN

◆ WM8960_AUDIO_INTF1_WL8_8BIT

◆ WM8960_CLK1_ADCDIV_BY_1

◆ WM8960_CLK1_ADCDIV_BY_1_5

◆ WM8960_CLK1_ADCDIV_BY_2

◆ WM8960_CLK1_ADCDIV_BY_3

◆ WM8960_CLK1_ADCDIV_BY_4

◆ WM8960_CLK1_ADCDIV_BY_5_5

◆ WM8960_CLK1_ADCDIV_BY_6

◆ WM8960_CLK1_CLKSEL_MCLK

◆ WM8960_CLK1_CLKSEL_PLL

◆ WM8960_CLK1_DACDIV_BY_1

◆ WM8960_CLK1_DACDIV_BY_1_5

◆ WM8960_CLK1_DACDIV_BY_2

◆ WM8960_CLK1_DACDIV_BY_3

◆ WM8960_CLK1_DACDIV_BY_4

◆ WM8960_CLK1_DACDIV_BY_5_5

◆ WM8960_CLK1_DACDIV_BY_6

◆ WM8960_CLK1_SYSCLKDIV_BY_1

◆ WM8960_CLK1_SYSCLKDIV_BY_2

◆ WM8960_CLK2_BCLKDIV_BY_11

◆ WM8960_CLK2_BCLKDIV_BY_12

◆ WM8960_CLK2_BCLKDIV_BY_16

◆ WM8960_CLK2_BCLKDIV_BY_1_5

◆ WM8960_CLK2_BCLKDIV_BY_2

◆ WM8960_CLK2_BCLKDIV_BY_22

◆ WM8960_CLK2_BCLKDIV_BY_24

◆ WM8960_CLK2_BCLKDIV_BY_3

◆ WM8960_CLK2_BCLKDIV_BY_32

◆ WM8960_CLK2_BCLKDIV_BY_4

◆ WM8960_CLK2_BCLKDIV_BY_5_5

◆ WM8960_CLK2_BCLKDIV_BY_6

◆ WM8960_CLK2_BCLKDIV_BY_8

◆ WM8960_CLK2_DCLKDIV_BY_12

◆ WM8960_CLK2_DCLKDIV_BY_16

◆ WM8960_CLK2_DCLKDIV_BY_2

◆ WM8960_CLK2_DCLKDIV_BY_3

◆ WM8960_CLK2_DCLKDIV_BY_4

◆ WM8960_CLK2_DCLKDIV_BY_6

◆ WM8960_CLK2_DCLKDIV_BY_8

◆ WM8960_CTR1_ADCHPD_DIS