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| | DSIBusSTM32 (int8_t rst, size_t width, size_t height, uint8_t laneNum, uint32_t laneMbps, uint32_t dpiClockKHz, const DSI_PLLInitTypeDef &pllInit, uint16_t *framebuffer) |
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| void | setVideoTiming (uint16_t hsyncPulseWidth, uint16_t hsyncBackPorch, uint16_t hsyncFrontPorch, uint16_t vsyncPulseWidth, uint16_t vsyncBackPorch, uint16_t vsyncFrontPorch) |
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| bool | begin () override |
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| void | end () override |
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| bool | writeCommand (uint8_t cmd, const uint8_t *param, size_t len) override |
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| bool | finishInit () override |
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| bool | drawBitmap (size_t x0, size_t y0, size_t x1, size_t y1, const uint8_t *rgb565) override |
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| virtual | ~IDSIBus ()=default |
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| virtual bool | begin ()=0 |
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| virtual void | end ()=0 |
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| virtual bool | writeCommand (uint8_t cmd, const uint8_t *param, size_t len)=0 |
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| virtual bool | finishInit ()=0 |
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| virtual bool | drawBitmap (size_t x0, size_t y0, size_t x1, size_t y1, const uint8_t *rgb565)=0 |
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IDSIBus backend for STM32 parts with a DSI host + LTDC (F469/ F479, F769/F779, H747/H757, U5x9, ...), built on STM32Cube HAL's HAL_DSI_* (command channel, adapted/video-mode DSI wrapper) and HAL_LTDC_* (the pixel-timing generator/framebuffer scanner DSI sits in front of on these parts - conceptually the same role ESP32-P4's DPI peripheral plays for DSIBusESP32).
UNVERIFIED ON REAL HARDWARE - unlike DSIBusESP32 (whose ESP32-P4 DPI path is exercised by boards this library ships examples for), no STM32-DSI board has been used to test this class. The DSI-video-timing math (HSA/HBP/HLINE expressed in DSI lane-byte-clock cycles, derived from the pixel-domain porches via the standard <pixels> * laneByteClk_kHz / dpiClock_kHz conversion) and the LTDC accumulated-timing fields follow the pattern used throughout ST's own DSI panel BSPs (e.g. the OTM8009A driver shipped with the STM32F769I-Discovery/STM32H747I-Discovery BSPs) - treat it as a documented starting point for board bring-up, not a guarantee.
Deliberately NOT in scope here: the DSI PHY PLL (dsiPllInit - NDIV/IDF/ ODF) and the LTDC pixel clock (normally routed off RCC PLL3 on these parts). Both depend on the board's external oscillator and are ordinarily produced by STM32CubeMX's generated SystemClock_Config() - this class takes the already-computed DSI_PLLInitTypeDef and LTDC pixel clock (in kHz) as constructor inputs rather than guessing at divisors that would silently be wrong for any board other than the one they were tuned for.
Only a single framebuffer is used (no double-buffering), same tradeoff DSIBusESP32 accepts - see that class's doc comment.