arduino-audio-driver
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AD1938.h
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1/* AD1938 Audio Codec control library
2 *
3 * Copyright (c) 2017, Yasmeen Sultana
4 * Copyright (c) 2024, Phil Schatzmann
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice, development funding notice, and this permission
14 * notice shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#ifdef ARDUINO
26#pragma once
27#include <SPI.h>
28
29#include "Codecs/CodecConstants.h"
30#include "DriverCommon.h"
31#include "Platforms/API_GPIO.h"
32
33/*
34reference
35http://www.analog.com/media/en/technical-documentation/data-sheets/AD1938.pdf
36http://www.analog.com/media/en/technical-documentation/application-notes/AN-1365.pdf
37*/
38/* SPI 3 byte register format
39----------------------------------------------
40|Global Address |R/W |Register Address |Data |
41----------------------------------------------
42|23:17 |16 |15:8 | 7:0|
43----------------------------------------------
44Address Register
450 PLL and Clock Control 0
461 PLL and Clock Control 1
472 DAC Control 0
483 DAC Control 1
494 DAC Control 2
505 DAC individual channel mutes
516 DAC L1 volume control
527 DAC R1 volume control
538 DAC L2 volume control
549 DAC R2 volume control
5510 DAC L3 volume control
5611 DAC R3 volume control
5712 DAC L4 volume control
5813 DAC R4 volume control
5914 ADC Control 0
6015 ADC Control 1
6116 ADC Control 2
62*/
63
64
65namespace audio_driver {
66
75class AD1938 {
76 public:
77 static constexpr uint8_t AD1938_GLOBAL_ADDRESS = 0x04;
78 static constexpr uint8_t AD1938_WRITE_ADDRESS = (AD1938_GLOBAL_ADDRESS << 1);
79 static constexpr uint8_t AD1938_READ_ADDRESS = ((AD1938_GLOBAL_ADDRESS << 1) | 1);
80 static constexpr int AD1938_SPI_WRITE_BYTE_COUNT = 3;
81 static constexpr int AD1938_SPI_READ_BYTE_COUNT = 2;
82 static constexpr uint8_t AD1938_PLL_CLK_CTRL0 = 0x00;
83 static constexpr uint8_t DIS_ADC_DAC = 0x00;
84 static constexpr uint8_t ENA_ADC_DAC = 0x80;
85 static constexpr uint8_t PLL_IN_MCLK = 0x00;
86 static constexpr uint8_t PLL_IN_DLRCLK = 0x20;
87 static constexpr uint8_t PLL_IN_ALRCLK = 0x40;
88 static constexpr uint8_t MCLK_OUT_XTAL = 0x00;
89 static constexpr uint8_t MCLK_OUT_256FS = 0x08;
90 static constexpr uint8_t MCLK_OUT_512FS = 0x10;
91 static constexpr uint8_t MCLK_OUT_OFF = 0x18;
92 static constexpr uint8_t INPUT256 = 0x00;
93 static constexpr uint8_t INPUT384 = 0x02;
94 static constexpr uint8_t INPUT512 = 0x04;
95 static constexpr uint8_t INPUT768 = 0x06;
96 static constexpr uint8_t PLL_PWR_UP = 0x00;
97 static constexpr uint8_t PLL_PWR_DWN = 0x01;
98 static constexpr uint8_t AD1938_PLL_CLK_CTRL1 = 0x01;
99 static constexpr uint8_t AD1938_PLL_LOCK = 0x08;
100 static constexpr uint8_t DIS_VREF = 0x04;
101 static constexpr uint8_t ENA_VREF = 0x00;
102 static constexpr uint8_t ADC_CLK_PLL = 0x00;
103 static constexpr uint8_t ADC_CLK_MCLK = 0x20;
104 static constexpr uint8_t DAC_CLK_PLL = 0x00;
105 static constexpr uint8_t DAC_CLK_MCLK = 0x01;
106 static constexpr uint8_t AD1938_DAC_CTRL0 = 0x02;
107 static constexpr uint8_t DAC_FMT_I2S = 0x00;
108 static constexpr uint8_t DAC_FMT_TDM = 0x40;
109 static constexpr uint8_t DAC_FMT_AUX = 0x80;
110 static constexpr uint8_t DAC_FMT_DUALTDM = 0xc0;
111 static constexpr uint8_t DAC_BCLK_DLY_1 = 0x00;
112 static constexpr uint8_t DAC_BCLK_DLY_0 = 0x08;
113 static constexpr uint8_t DAC_BCLK_DLY_8 = 0x01;
114 static constexpr uint8_t DAC_BCLK_DLY_12 = 0x18;
115 static constexpr uint8_t DAC_BCLK_DLY_16 = 0x20;
116 static constexpr uint8_t DAC_SR_48K = 0x00;
117 static constexpr uint8_t DAC_SR_96K = 0x02;
118 static constexpr uint8_t DAC_SR_192K = 0x04;
119 static constexpr uint8_t DAC_PWR_UP = 0x00;
120 static constexpr uint8_t DAC_PWR_DWN = 0x01;
121 static constexpr uint8_t AD1938_DAC_CTRL1 = 0x03;
122 static constexpr uint8_t DAC_BCLK_POL_NORM = 0x00;
123 static constexpr uint8_t DAC_BCLK_POL_INV = 0x80;
124 static constexpr uint8_t DAC_BCLK_SRC_PIN = 0x00;
125 static constexpr uint8_t DAC_BCLK_SRC_INTERNAL = 0x40;
126 static constexpr uint8_t DAC_BCLK_SLAVE = 0x00;
127 static constexpr uint8_t DAC_BCLK_MASTER = 0x20;
128 static constexpr uint8_t DAC_LRCLK_SLAVE = 0x00;
129 static constexpr uint8_t DAC_LRCLK_MASTER = 0x10;
130 static constexpr uint8_t DAC_LRCLK_POL_NORM = 0x00;
131 static constexpr uint8_t DAC_LRCLK_POL_INV = 0x08;
132 static constexpr uint8_t DAC_CHANNELS_2 = 0x00;
133 static constexpr uint8_t DAC_CHANNELS_4 = 0x02;
134 static constexpr uint8_t DAC_CHANNELS_8 = 0x04;
135 static constexpr uint8_t DAC_CHANNELS_16 = 0x06;
136 static constexpr uint8_t DAC_LATCH_MID = 0x00;
137 static constexpr uint8_t DAC_LATCH_END = 0x01;
138 static constexpr uint8_t AD1938_DAC_CTRL2 = 0x04;
139 static constexpr uint8_t DAC_OUT_POL_NORM = 0x00;
140 static constexpr uint8_t DAC_OUT_POL_INV = 0x20;
141 static constexpr uint8_t DAC_WIDTH_24 = 0x00;
142 static constexpr uint8_t DAC_WIDTH_20 = 0x08;
143 static constexpr uint8_t DAC_WIDTH_16 = 0x18;
144 static constexpr uint8_t DAC_DEEMPH_FLAT = 0x00;
145 static constexpr uint8_t DAC_DEEMPH_48K = 0x02;
146 static constexpr uint8_t DAC_DEEMPH_44_1K = 0x04;
147 static constexpr uint8_t DAC_DEEMPH_32K = 0x06;
148 static constexpr uint8_t DAC_UNMUTE_ALL = 0x00;
149 static constexpr uint8_t DAC_MUTE_ALL = 0x01;
150 static constexpr uint8_t AD1938_DAC_CHNL_MUTE = 0x05;
151 static constexpr uint8_t DACMUTE_R4 = 0x80;
152 static constexpr uint8_t DACMUTE_L4 = 0x40;
153 static constexpr uint8_t DACMUTE_R3 = 0x20;
154 static constexpr uint8_t DACMUTE_L3 = 0x10;
155 static constexpr uint8_t DACMUTE_R2 = 0x08;
156 static constexpr uint8_t DACMUTE_L2 = 0x04;
157 static constexpr uint8_t DACMUTE_R1 = 0x02;
158 static constexpr uint8_t DACMUTE_L1 = 0x01;
159 static constexpr uint8_t DACVOL_MIN = 0xFF;
160 static constexpr uint8_t DACVOL_LOW = 0xC0;
161 static constexpr uint8_t DACVOL_MED = 0x80;
162 static constexpr uint8_t DACVOL_HI = 0x40;
163 static constexpr uint8_t DACVOL_MAX = 0x00;
164 static constexpr uint8_t DACVOL_MASK = 0xFF;
165 static constexpr uint8_t AD1938_DAC_L1_VOL = 0x06;
166 static constexpr uint8_t AD1938_DAC_R1_VOL = 0x07;
167 static constexpr uint8_t AD1938_DAC_L2_VOL = 0x08;
168 static constexpr uint8_t AD1938_DAC_R2_VOL = 0x09;
169 static constexpr uint8_t AD1938_DAC_L3_VOL = 0x0a;
170 static constexpr uint8_t AD1938_DAC_R3_VOL = 0x0b;
171 static constexpr uint8_t AD1938_DAC_L4_VOL = 0x0c;
172 static constexpr uint8_t AD1938_DAC_R4_VOL = 0x0d;
173 static constexpr uint8_t AD1938_ADC_CTRL0 = 0x0e;
174 static constexpr uint8_t ADC_SR_48K = 0x00;
175 static constexpr uint8_t ADC_SR_96K = 0x40;
176 static constexpr uint8_t ADC_SR_192K = 0x80;
177 static constexpr uint8_t ADC_R2_UNMUTE = 0x00;
178 static constexpr uint8_t ADC_R2_MUTE = 0x20;
179 static constexpr uint8_t ADC_L2_UNMUTE = 0x00;
180 static constexpr uint8_t ADC_L2_MUTE = 0x10;
181 static constexpr uint8_t ADC_R1_UNMUTE = 0x00;
182 static constexpr uint8_t ADC_R1_MUTE = 0x08;
183 static constexpr uint8_t ADC_L1_UNMUTE = 0x00;
184 static constexpr uint8_t ADC_L1_MUTE = 0x04;
185 static constexpr uint8_t ADC_HP_FILT_OFF = 0x00;
186 static constexpr uint8_t ADC_HP_FILT_ON = 0x02;
187 static constexpr uint8_t ADC_PWR_UP = 0x00;
188 static constexpr uint8_t ADC_PWR_DWN = 0x01;
189 static constexpr uint8_t AD1938_ADC_CTRL1 = 0x0f;
190 static constexpr int AD1938_SPI_CLK_FREQ = 1000000;
191 static constexpr uint8_t ADC_LATCH_MID = 0x00;
192 static constexpr uint8_t ADC_LATCH_END = 0x80;
193 static constexpr uint8_t ADC_FMT_I2S = 0x00;
194 static constexpr uint8_t ADC_FMT_TDM = 0x20;
195 static constexpr uint8_t ADC_FMT_AUX = 0x40;
196 static constexpr uint8_t ADC_BCLK_DLY_1 = 0x00;
197 static constexpr uint8_t ADC_BCLK_DLY_0 = 0x04;
198 static constexpr uint8_t ADC_BCLK_DLY_8 = 0x08;
199 static constexpr uint8_t ADC_BCLK_DLY_12 = 0x0c;
200 static constexpr uint8_t ADC_BCLK_DLY_16 = 0x10;
201 static constexpr uint8_t ADC_WIDTH_24 = 0x00;
202 static constexpr uint8_t ADC_WIDTH_20 = 0x01;
203 static constexpr uint8_t ADC_WIDTH_16 = 0x03;
204 static constexpr uint8_t AD1938_ADC_CTRL2 = 0x10;
205 static constexpr uint8_t ADC_BCLK_SRC_PIN = 0x00;
206 static constexpr uint8_t ADC_BCLK_SRC_INTERNAL = 0x80;
207 static constexpr uint8_t ADC_BCLK_SLAVE = 0x00;
208 static constexpr uint8_t ADC_BCLK_MASTER = 0x40;
209 static constexpr uint8_t ADC_CHANNELS_2 = 0x00;
210 static constexpr uint8_t ADC_CHANNELS_4 = 0x10;
211 static constexpr uint8_t ADC_CHANNELS_8 = 0x20;
212 static constexpr uint8_t ADC_CHANNELS_16 = 0x30;
213 static constexpr uint8_t ADC_LRCLK_SLAVE = 0x00;
214 static constexpr uint8_t ADC_LRCLK_MASTER = 0x08;
215 static constexpr uint8_t ADC_LRCLK_POL_NORM = 0x00;
216 static constexpr uint8_t ADC_LRCLK_POL_INV = 0x04;
217 static constexpr uint8_t ADC_BCLK_POL_NORM = 0x00;
218 static constexpr uint8_t ADC_BCLK_POL_INV = 0x02;
219 static constexpr uint8_t ADC_LRCLK_FMT_50_50 = 0x00;
220 static constexpr uint8_t ADC_LRCLK_FMT_PULSE = 0x01;
221 bool begin(API_GPIO& gpio, codec_config_t cfg, int clatchPin, int resetPin,
222 SPIClass& spi = SPI);
223
224 bool end() {
225 setMute(true);
226 return disable();
227 }
228
229 bool enable(void);
230
231 bool disable(void);
232
233 bool setVolume(float volume) {
234 int vol = scaleVolume(volume);
235 for (int j = 0; j < 4; j++) setVolumeDAC(j, vol);
236 return true;
237 }
238 bool setVolume(int dac, float volume) {
239 return setVolumeDAC(dac, scaleVolume(volume));
240 }
241 bool setVolume(int volume) {
242 for (int j = 0; j < 4; j++) setVolumeDAC(j, volume);
243 return true;
244 }
245 bool setVolumeDAC(int dac, int volume);
246
247 bool setMuteADC(bool mute);
248
249 bool setMuteDAC(bool mute);
250
251 bool setMute(bool mute) { return setMuteADC(mute) && setMuteDAC(mute); }
252
253 protected:
254 codec_config_t cfg;
255 int ad1938_clatch_pin;
256 int ad1938_reset_pin;
257 SPIClass* p_spi = nullptr;
258 unsigned char dac_fs = 0;
259 unsigned char adc_fs = 0;
260 unsigned char dac_mode = 0;
261 unsigned char adc_mode = 0;
262 unsigned char dac_wl = 0;
263 unsigned char adc_wl = 0;
264 unsigned char dac_channels = 0;
265 unsigned char adc_channels = 0;
266 API_GPIO* p_gpio = nullptr;
267
268 bool config();
269 bool configMaster();
270 bool configSlave();
271 bool spi_write_reg(unsigned char reg, unsigned char val);
272 unsigned char spi_read_reg(unsigned char reg);
273 bool isPllLocked();
274 int scaleVolume(float volume) {
275 int vol = (1.0 - volume) * 255;
276 if (vol < 0) vol = 0;
277 if (vol > 255) vol = 255;
278 return vol;
279 }
280};
281
282inline bool AD1938::begin(API_GPIO& gpio, codec_config_t configVal,
283 int clatchPin, int resetPin, SPIClass& spi) {
284 ad1938_clatch_pin = clatchPin;
285 ad1938_reset_pin = resetPin;
286 cfg = configVal;
287 p_spi = &spi;
288 p_gpio = &gpio;
289
290 // setup pins
291 p_gpio->pinMode(ad1938_clatch_pin, OUTPUT);
292 p_gpio->pinMode(ad1938_reset_pin, OUTPUT);
293
294 // reset codec
295 p_gpio->digitalWrite(ad1938_reset_pin, LOW);
296 delayMs(200);
297 p_gpio->digitalWrite(ad1938_reset_pin, HIGH);
298 delayMs(400); // wait for 300ms to load the code
299
300 // setup basic information from codec_config_t
301 config();
302
303 return true;
304}
305
306inline unsigned char AD1938::spi_read_reg(unsigned char reg) {
307 unsigned char result = 0;
308 unsigned char data[AD1938_SPI_WRITE_BYTE_COUNT];
309
310 data[0] = AD1938_READ_ADDRESS;
311 data[1] = reg;
312 data[2] = 0x0;
313
314 // and configure settings
315 p_spi->beginTransaction(
316 SPISettings(AD1938_SPI_CLK_FREQ, MSBFIRST, SPI_MODE3));
317 // take the chip select low to select the device:
318 p_gpio->digitalWrite(ad1938_clatch_pin, LOW);
319
320 p_spi->transfer(
321 &data[0],
322 AD1938_SPI_READ_BYTE_COUNT); // Send register location , read byte is 2
323
324 // send a value of 0 to read the first byte returned:
325 result = (unsigned char)p_spi->transfer(0x00);
326
327 // take the chip select high to de-select:
328 p_gpio->digitalWrite(ad1938_clatch_pin, HIGH);
329 // release control of the SPI port
330 p_spi->endTransaction();
331
332 return (result);
333}
334
335inline bool AD1938::spi_write_reg(unsigned char reg, unsigned char val) {
336 unsigned char data[AD1938_SPI_WRITE_BYTE_COUNT];
337
338 /*fill the buffer as per AD1938 format*/
339 data[0] = AD1938_WRITE_ADDRESS;
340 data[1] = reg;
341 data[2] = val;
342
343 // and configure settings
344 p_spi->beginTransaction(SPISettings(
345 AD1938_SPI_CLK_FREQ, MSBFIRST,
346 SPI_MODE3)); // 3
347 // take the chip select low to select the device:
348 p_gpio->digitalWrite(ad1938_clatch_pin, LOW);
349
350 p_spi->transfer(&data[0], AD1938_SPI_WRITE_BYTE_COUNT);
351 // take the chip select high to de-select:
352 p_gpio->digitalWrite(ad1938_clatch_pin, HIGH);
353 // release control of the SPI port
354 p_spi->endTransaction();
355
356 return true;
357}
358
359inline bool AD1938::config() {
360 switch (cfg.i2s.rate) {
361 case RATE_32K:
362 case RATE_44K:
363 case RATE_48K: {
364 dac_fs = DAC_SR_48K;
365 adc_fs = ADC_SR_48K;
366 } break;
367 case RATE_64K:
368 case RATE_88K:
369 case RATE_96K: {
370 dac_fs = DAC_SR_96K;
371 adc_fs = ADC_SR_96K;
372 } break;
373 case RATE_128K:
374 case RATE_176K:
375 case RATE_192K: {
376 dac_fs = DAC_SR_192K;
377 adc_fs = ADC_SR_192K;
378 } break;
379 default: {
380 dac_fs = DAC_SR_48K;
381 adc_fs = ADC_SR_48K;
382 }
383 }
384
385 switch (cfg.i2s.bits) {
386 case BIT_LENGTH_16BITS: {
387 dac_wl = DAC_WIDTH_16;
388 adc_wl = ADC_WIDTH_16;
389
390 } break;
391 case BIT_LENGTH_20BITS: {
392 dac_wl = DAC_WIDTH_20;
393 adc_wl = ADC_WIDTH_20;
394
395 } break;
396 case BIT_LENGTH_24BITS: {
397 dac_wl = DAC_WIDTH_24;
398 adc_wl = ADC_WIDTH_24;
399 }
400
401 break;
402
403 default: {
404 dac_wl = DAC_WIDTH_24;
405 adc_wl = ADC_WIDTH_24;
406 }
407 }
408
409 switch (cfg.i2s.channels) {
410 case CHANNELS2: {
411 dac_mode = DAC_FMT_I2S;
412 adc_mode = ADC_FMT_I2S;
413 dac_channels = DAC_CHANNELS_2;
414 adc_channels = ADC_CHANNELS_2;
415
416 } break;
417 case CHANNELS8: {
418 dac_mode = DAC_FMT_TDM;
419 adc_mode = ADC_FMT_TDM;
420 dac_channels = DAC_CHANNELS_8;
421 adc_channels = ADC_CHANNELS_8;
422
423 } break;
424 case CHANNELS16: {
425 dac_mode = DAC_FMT_TDM;
426 adc_mode = ADC_FMT_TDM;
427 dac_channels = DAC_CHANNELS_16;
428 adc_channels = ADC_CHANNELS_16;
429
430 } break;
431 default: {
432 dac_mode = DAC_FMT_I2S;
433 adc_mode = ADC_FMT_I2S;
434 dac_channels = DAC_CHANNELS_2;
435 adc_channels = ADC_CHANNELS_2;
436 }
437 }
438
439 if (cfg.i2s.mode == MODE_SLAVE) {
440 configSlave();
441 } else {
442 configMaster();
443 }
444 return true;
445}
446
447inline bool AD1938::configMaster() {
448 // 0 PLL and Clock Control 0
449 spi_write_reg(AD1938_PLL_CLK_CTRL0, (DIS_ADC_DAC | INPUT512 | PLL_IN_MCLK |
450 MCLK_OUT_XTAL | PLL_PWR_DWN));
451
452 // 1 PLL and Clock Control 1
453 spi_write_reg(AD1938_PLL_CLK_CTRL1, (DAC_CLK_MCLK | ADC_CLK_MCLK | ENA_VREF));
454
455 // 2 DAC Control 0
456 spi_write_reg(AD1938_DAC_CTRL0,
457 (dac_mode | DAC_BCLK_DLY_1 | dac_fs | DAC_PWR_UP));
458
459 // 3 DAC Control 1
460 spi_write_reg(AD1938_DAC_CTRL1,
461 (DAC_BCLK_SRC_INTERNAL | DAC_BCLK_SLAVE | DAC_LRCLK_SLAVE |
462 DAC_LRCLK_POL_NORM | dac_channels | DAC_LATCH_MID));
463
464 // 4 DAC Control 2
465 spi_write_reg(AD1938_DAC_CTRL2, dac_wl);
466
467 // 5 DAC individual channel mutes
468 spi_write_reg(AD1938_DAC_CHNL_MUTE, 0x00); /*unmute*/
469
470 setVolume(DACVOL_MAX);
471
472 // 14 ADC Control 0
473 spi_write_reg(AD1938_ADC_CTRL0, adc_fs);
474
475 // 15 ADC Control 1
476 spi_write_reg(AD1938_ADC_CTRL1,
477 (ADC_LATCH_MID | adc_mode | ADC_BCLK_DLY_1 | adc_wl));
478
479 // 16 ADC Control 2
480 spi_write_reg(AD1938_ADC_CTRL2,
481 (ADC_BCLK_SRC_INTERNAL | ADC_BCLK_MASTER | adc_channels |
482 ADC_LRCLK_MASTER | ADC_LRCLK_FMT_50_50 | ADC_LRCLK_POL_NORM |
483 ADC_BCLK_POL_NORM));
484 return true;
485}
486
487inline bool AD1938::configSlave() {
488 // 0 PLL and Clock Control 0
489 spi_write_reg(AD1938_PLL_CLK_CTRL0, (DIS_ADC_DAC | INPUT512 | PLL_IN_ALRCLK |
490 MCLK_OUT_OFF | PLL_PWR_DWN));
491
492 // 1 PLL and Clock Control 1
493 spi_write_reg(AD1938_PLL_CLK_CTRL1, (DAC_CLK_PLL | ADC_CLK_PLL | ENA_VREF));
494
495 // 2 DAC Control 0
496 spi_write_reg(AD1938_DAC_CTRL0,
497 (dac_mode | DAC_BCLK_DLY_1 | dac_fs | DAC_PWR_UP));
498
499 // 3 DAC Control 1
500 spi_write_reg(AD1938_DAC_CTRL1,
501 (DAC_BCLK_SRC_PIN | DAC_BCLK_SLAVE | DAC_LRCLK_SLAVE |
502 DAC_LRCLK_POL_NORM | dac_channels | DAC_LATCH_MID));
503 // 4 DAC Control 2
504 spi_write_reg(AD1938_DAC_CTRL2, dac_wl);
505
506 // 5 DAC individual channel mutes
507 spi_write_reg(AD1938_DAC_CHNL_MUTE, 0x00); /*mute*/
508
509 setVolume(DACVOL_MAX);
510
511 // 14 ADC Control 0
512 spi_write_reg(AD1938_ADC_CTRL0, adc_fs);
513
514 // 15 ADC Control 1
515 spi_write_reg(AD1938_ADC_CTRL1,
516 (ADC_LATCH_MID | adc_mode | ADC_BCLK_DLY_0 | adc_wl));
517
518 // 16 ADC Control 2
519 spi_write_reg(
520 AD1938_ADC_CTRL2,
521 (ADC_BCLK_SRC_PIN | ADC_BCLK_SLAVE | adc_channels | ADC_LRCLK_SLAVE |
522 ADC_LRCLK_FMT_50_50 | ADC_LRCLK_POL_NORM | ADC_BCLK_POL_NORM));
523 return true;
524}
525
526inline bool AD1938::isPllLocked(void) {
527 return ((spi_read_reg(AD1938_PLL_CLK_CTRL1) >> 3) & 0x1);
528}
529
530inline bool AD1938::enable(void) {
531 if (cfg.i2s.mode == MODE_SLAVE) {
532 spi_write_reg(
533 AD1938_PLL_CLK_CTRL0,
534 (ENA_ADC_DAC | INPUT512 | PLL_IN_DLRCLK | MCLK_OUT_OFF | PLL_PWR_UP));
535 } else {
536 spi_write_reg(AD1938_PLL_CLK_CTRL0, (ENA_ADC_DAC | INPUT512 | PLL_IN_MCLK |
537 MCLK_OUT_XTAL | PLL_PWR_UP));
538 }
539
540 spi_write_reg(AD1938_DAC_CHNL_MUTE, 0); /*un mute*/
541
542 return true;
543}
544
545inline bool AD1938::disable(void) {
546 unsigned char reg_value;
547 reg_value = spi_read_reg(AD1938_PLL_CLK_CTRL0);
548 reg_value = (reg_value & 0x7e); /*mask the last and first bits*/
549 spi_write_reg(AD1938_PLL_CLK_CTRL0, (DIS_ADC_DAC | reg_value | PLL_PWR_DWN));
550
551 reg_value = spi_read_reg(AD1938_DAC_CTRL0);
552
553 spi_write_reg(AD1938_DAC_CTRL0, ((reg_value & 0xfe) | DAC_PWR_DWN));
554
555 reg_value = spi_read_reg(AD1938_ADC_CTRL0);
556
557 spi_write_reg(AD1938_ADC_CTRL0, ((reg_value & 0xfe) | ADC_PWR_DWN));
558
559 return true;
560}
561
562inline bool AD1938::setVolumeDAC(int dac_num, int volume) {
563 if (dac_num < 0 || dac_num > 3) return false;
564 spi_write_reg(AD1938_DAC_L1_VOL + dac_num * 2, volume);
565 spi_write_reg(AD1938_DAC_R1_VOL + dac_num * 2, volume);
566
567 return true;
568}
569
570inline bool AD1938::setMuteDAC(bool mute) {
571 if (mute == true) {
572 spi_write_reg(AD1938_DAC_CHNL_MUTE, 0xff); /*mute*/
573 } else {
574 spi_write_reg(AD1938_DAC_CHNL_MUTE, 00); /*unmute*/
575 }
576 return true;
577}
578
579inline bool AD1938::setMuteADC(bool mute) {
580 unsigned char reg_value;
581 reg_value = spi_read_reg(AD1938_ADC_CTRL0);
582 if (mute == true) {
583 spi_write_reg(AD1938_ADC_CTRL0, (reg_value & 0xc3) | 0x3c); /*mute*/
584 } else {
585 spi_write_reg(AD1938_ADC_CTRL0, (reg_value & 0xc3)); /*unmute*/
586 }
587 return true;
588}
589
590} // namespace audio_driver
591
592#endif
API_GPIO.h
HIGH
#define HIGH
Definition DriverCommon.h:35
OUTPUT
#define OUTPUT
Definition DriverCommon.h:44
LOW
#define LOW
Definition DriverCommon.h:38
audio_driver
Namespace for audio driver components.
Definition AudioBoard.h:5
audio_driver::delayMs
void delayMs(unsigned long ms)
Definition API_Delay.h:19
audio_driver::BIT_LENGTH_24BITS
@ BIT_LENGTH_24BITS
Definition DriverCommon.h:240
audio_driver::BIT_LENGTH_20BITS
@ BIT_LENGTH_20BITS
Definition DriverCommon.h:239
audio_driver::BIT_LENGTH_16BITS
@ BIT_LENGTH_16BITS
Definition DriverCommon.h:237
audio_driver::RATE_44K
@ RATE_44K
Definition DriverCommon.h:220
audio_driver::RATE_128K
@ RATE_128K
Definition DriverCommon.h:225
audio_driver::RATE_88K
@ RATE_88K
Definition DriverCommon.h:223
audio_driver::RATE_176K
@ RATE_176K
Definition DriverCommon.h:226
audio_driver::RATE_32K
@ RATE_32K
Definition DriverCommon.h:219
audio_driver::RATE_96K
@ RATE_96K
Definition DriverCommon.h:224
audio_driver::RATE_64K
@ RATE_64K
Definition DriverCommon.h:222
audio_driver::RATE_48K
@ RATE_48K
Definition DriverCommon.h:221
audio_driver::RATE_192K
@ RATE_192K
Definition DriverCommon.h:227
audio_driver::CHANNELS2
@ CHANNELS2
Definition DriverCommon.h:275
audio_driver::CHANNELS16
@ CHANNELS16
Definition DriverCommon.h:278
audio_driver::CHANNELS8
@ CHANNELS8
Definition DriverCommon.h:277
audio_driver::MODE_SLAVE
@ MODE_SLAVE
Definition DriverCommon.h:204
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